📄 spi_master.rpt
字号:
uc_intrface_rcv_full_reset 5 5
Signal Total Total User
Name Pts Inps Assignment
uc_intrface_spien 4 5
uc_intrface_spierr 4 4
uc_intrface_spierr_N1 2 2
uc_intrface_spierr_reset 4 5
uc_intrface_spirr<0> 4 5
uc_intrface_spirr<1> 4 5
uc_intrface_spirr<2> 4 5
uc_intrface_spirr<3> 4 5
uc_intrface_spirr<4> 4 5
uc_intrface_spirr<5> 4 5
uc_intrface_spirr<6> 4 5
uc_intrface_spirr<7> 4 5
uc_intrface_spissr<0> 4 5
uc_intrface_spissr<1> 4 5
uc_intrface_spissr<2> 4 5
uc_intrface_spissr<3> 4 5
uc_intrface_spissr<4> 4 5
uc_intrface_spissr<5> 4 5
uc_intrface_spissr<6> 4 5
uc_intrface_spissr<7> 4 5
uc_intrface_spitr<0> 4 5
uc_intrface_spitr<1> 4 5
uc_intrface_spitr<2> 4 5
uc_intrface_spitr<3> 4 5
uc_intrface_spitr<4> 4 5
uc_intrface_spitr<5> 4 5
uc_intrface_spitr<6> 4 5
uc_intrface_spitr<7> 4 5
uc_intrface_ssel_en 3 4
uc_intrface_start 4 5
uc_intrface_stat_en 3 4
uc_intrface_xmit_empty_reset 5 5
uc_intrface_xmit_en 3 5
** 16 Inputs **
Signal I/O User
Name STD Assignment
addr<0> LVCMOS18
addr<1> LVCMOS18
addr<2> LVCMOS18
addr<3> LVCMOS18
addr<4> LVCMOS18
addr<5> LVCMOS18
addr<6> LVCMOS18
addr<7> LVCMOS18
ale_n LVCMOS18
clk LVCMOS18
miso LVCMOS18
psen_n LVCMOS18
rd_n LVCMOS18
reset LVCMOS18
ss_in_n LVCMOS18
wr_n LVCMOS18
******************************* Equations ********************************
********** UnMapped Logic **********
** Outputs **
FDCPE_sck: FDCPE port map (sck_I,sck,clk,NOT uc_intrface_spien,'0','1');
sck <= ((spi_intrface_SCK_GEN_Mmux__mux0005_Result13)
OR (spi_intrface_SCK_GEN_Mmux__mux0005_Result15));
sck <= sck_I when sck_OE = '1' else 'Z';
sck_OE <= spi_intrface_spi_ctrl_sm_ss_in_int;
FDCPE_rcv_full: FDCPE port map (rcv_full,uc_intrface_rcv_full_reset,clk,NOT uc_intrface_spien,'0',spi_intrface_spi_ctrl_sm__not0003);
FDCPE_ss_n0: FDCPE port map (ss_n_I(0),ss_n(0),NOT clk,'0',NOT uc_intrface_spien,'1');
ss_n(0) <= ((NOT uc_intrface_spissr(0))
OR (ss_n_int));
ss_n(0) <= ss_n_I(0) when ss_n_OE(0) = '1' else 'Z';
ss_n_OE(0) <= spi_intrface_spi_ctrl_sm_ss_in_int;
FDCPE_ss_n1: FDCPE port map (ss_n_I(1),ss_n(1),NOT clk,'0',NOT uc_intrface_spien,'1');
ss_n(1) <= ((NOT uc_intrface_spissr(1))
OR (ss_n_int));
ss_n(1) <= ss_n_I(1) when ss_n_OE(1) = '1' else 'Z';
ss_n_OE(1) <= spi_intrface_spi_ctrl_sm_ss_in_int;
FDCPE_ss_n2: FDCPE port map (ss_n_I(2),ss_n(2),NOT clk,'0',NOT uc_intrface_spien,'1');
ss_n(2) <= ((NOT uc_intrface_spissr(2))
OR (ss_n_int));
ss_n(2) <= ss_n_I(2) when ss_n_OE(2) = '1' else 'Z';
ss_n_OE(2) <= spi_intrface_spi_ctrl_sm_ss_in_int;
FDCPE_ss_n3: FDCPE port map (ss_n_I(3),ss_n(3),NOT clk,'0',NOT uc_intrface_spien,'1');
ss_n(3) <= ((NOT uc_intrface_spissr(3))
OR (ss_n_int));
ss_n(3) <= ss_n_I(3) when ss_n_OE(3) = '1' else 'Z';
ss_n_OE(3) <= spi_intrface_spi_ctrl_sm_ss_in_int;
FDCPE_ss_n4: FDCPE port map (ss_n_I(4),ss_n(4),NOT clk,'0',NOT uc_intrface_spien,'1');
ss_n(4) <= ((NOT uc_intrface_spissr(4))
OR (ss_n_int));
ss_n(4) <= ss_n_I(4) when ss_n_OE(4) = '1' else 'Z';
ss_n_OE(4) <= spi_intrface_spi_ctrl_sm_ss_in_int;
FDCPE_ss_n5: FDCPE port map (ss_n_I(5),ss_n(5),NOT clk,'0',NOT uc_intrface_spien,'1');
ss_n(5) <= ((NOT uc_intrface_spissr(5))
OR (ss_n_int));
ss_n(5) <= ss_n_I(5) when ss_n_OE(5) = '1' else 'Z';
ss_n_OE(5) <= spi_intrface_spi_ctrl_sm_ss_in_int;
FDCPE_ss_n6: FDCPE port map (ss_n_I(6),ss_n(6),NOT clk,'0',NOT uc_intrface_spien,'1');
ss_n(6) <= ((NOT uc_intrface_spissr(6))
OR (ss_n_int));
ss_n(6) <= ss_n_I(6) when ss_n_OE(6) = '1' else 'Z';
ss_n_OE(6) <= spi_intrface_spi_ctrl_sm_ss_in_int;
FDCPE_ss_n7: FDCPE port map (ss_n_I(7),ss_n(7),NOT clk,'0',NOT uc_intrface_spien,'1');
ss_n(7) <= ((NOT uc_intrface_spissr(7))
OR (ss_n_int));
ss_n(7) <= ss_n_I(7) when ss_n_OE(7) = '1' else 'Z';
ss_n_OE(7) <= spi_intrface_spi_ctrl_sm_ss_in_int;
FDCPE_xmit_empty: FDCPE port map (xmit_empty,'1',spi_intrface_sck_1,spi_intrface_spi_ctrl_sm__xor0008,'0',spi_intrface_xmit_load);
FDCPE_mosi: FDCPE port map (mosi_I,spi_intrface_xmit_shift_reg_data_int(7),clk,NOT uc_intrface_spien,'0','1');
mosi <= mosi_I when mosi_OE = '1' else 'Z';
mosi_OE <= spi_intrface_spi_ctrl_sm_ss_in_int;
FDCPE_addr_data0: FDCPE port map (addr_data_I(0),addr_data(0),clk,NOT reset,'0',NOT uc_intrface__xor0012);
addr_data(0) <= ((uc_intrface__mux0021(0)1)
OR (uc_intrface__mux0021(0)12));
addr_data(0) <= addr_data_I(0) when addr_data_OE(0) = '1' else 'Z';
addr_data_OE(0) <= uc_intrface_data_oe;
FDCPE_addr_data1: FDCPE port map (addr_data_I(1),addr_data(1),clk,NOT reset,'0',NOT uc_intrface__xor0012);
addr_data(1) <= ((uc_intrface__mux0021(1)1)
OR (uc_intrface__mux0021(1)12));
addr_data(1) <= addr_data_I(1) when addr_data_OE(1) = '1' else 'Z';
addr_data_OE(1) <= uc_intrface_data_oe;
FDCPE_addr_data2: FDCPE port map (addr_data_I(2),addr_data(2),clk,NOT reset,'0',NOT uc_intrface__xor0012);
addr_data(2) <= ((uc_intrface__mux0021(2)1)
OR (uc_intrface__mux0021(2)15));
addr_data(2) <= addr_data_I(2) when addr_data_OE(2) = '1' else 'Z';
addr_data_OE(2) <= uc_intrface_data_oe;
FDCPE_addr_data3: FDCPE port map (addr_data_I(3),addr_data(3),clk,NOT reset,'0',NOT uc_intrface__xor0012);
addr_data(3) <= ((uc_intrface__mux0021(3)1)
OR (uc_intrface__mux0021(3)15));
addr_data(3) <= addr_data_I(3) when addr_data_OE(3) = '1' else 'Z';
addr_data_OE(3) <= uc_intrface_data_oe;
FDCPE_addr_data4: FDCPE port map (addr_data_I(4),addr_data(4),clk,NOT reset,'0',NOT uc_intrface__xor0012);
addr_data(4) <= ((uc_intrface__mux0021(4)1)
OR (uc_intrface__mux0021(4)15));
addr_data(4) <= addr_data_I(4) when addr_data_OE(4) = '1' else 'Z';
addr_data_OE(4) <= uc_intrface_data_oe;
FDCPE_addr_data5: FDCPE port map (addr_data_I(5),addr_data(5),clk,NOT reset,'0',NOT uc_intrface__xor0012);
addr_data(5) <= ((uc_intrface__mux0021(5)1)
OR (uc_intrface__mux0021(5)15));
addr_data(5) <= addr_data_I(5) when addr_data_OE(5) = '1' else 'Z';
addr_data_OE(5) <= uc_intrface_data_oe;
FDCPE_addr_data6: FDCPE port map (addr_data_I(6),addr_data(6),clk,NOT reset,'0',NOT uc_intrface__xor0012);
addr_data(6) <= ((uc_intrface__mux0021(6)1)
OR (uc_intrface__mux0021(6)15));
addr_data(6) <= addr_data_I(6) when addr_data_OE(6) = '1' else 'Z';
addr_data_OE(6) <= uc_intrface_data_oe;
FDCPE_addr_data7: FDCPE port map (addr_data_I(7),addr_data(7),clk,NOT reset,'0',NOT uc_intrface__xor0012);
addr_data(7) <= ((uc_intrface__mux0021(7)1)
OR (uc_intrface__mux0021(7)15));
addr_data(7) <= addr_data_I(7) when addr_data_OE(7) = '1' else 'Z';
addr_data_OE(7) <= uc_intrface_data_oe;
FDCPE_int_n: FDCPE port map (int_n,int_n_D,clk,'0',NOT reset,uc_intrface__not0021);
int_n_D <= ((NOT uc_intrface_rcv_full_reset)
OR (NOT uc_intrface_spierr_reset)
OR (NOT uc_intrface_xmit_empty_reset));
** Buried Nodes **
rcv_data(0) <= ((spi_intrface_rcv_shift_reg/shift_in1)
OR (spi_intrface_rcv_shift_reg/shift_in3));
FDCPE_rcv_data1: FDCPE port map (rcv_data(1),rcv_data_D(1),sck.PIN,spi_intrface_rcv_shift_reg/_xor0000,'0',NOT ss_n_int);
rcv_data_D(1) <= ((spi_intrface_rcv_shift_reg/shift_in1)
OR (spi_intrface_rcv_shift_reg/shift_in3));
FDCPE_rcv_data2: FDCPE port map (rcv_data(2),rcv_data(1),sck.PIN,spi_intrface_rcv_shift_reg/_xor0000,'0',NOT ss_n_int);
FDCPE_rcv_data3: FDCPE port map (rcv_data(3),rcv_data(2),sck.PIN,spi_intrface_rcv_shift_reg/_xor0000,'0',NOT ss_n_int);
FDCPE_rcv_data4: FDCPE port map (rcv_data(4),rcv_data(3),sck.PIN,spi_intrface_rcv_shift_reg/_xor0000,'0',NOT ss_n_int);
FDCPE_rcv_data5: FDCPE port map (rcv_data(5),rcv_data(4),sck.PIN,spi_intrface_rcv_shift_reg/_xor0000,'0',NOT ss_n_int);
FDCPE_rcv_data6: FDCPE port map (rcv_data(6),rcv_data(5),sck.PIN,spi_intrface_rcv_shift_reg/_xor0000,'0',NOT ss_n_int);
FDCPE_rcv_data7: FDCPE port map (rcv_data(7),rcv_data(6),sck.PIN,spi_intrface_rcv_shift_reg/_xor0000,'0',NOT ss_n_int);
rcv_load <= (NOT ss_n_int AND spi_intrface_rcv_shift_reg/_and000015);
spi_intrface_SCK_GEN_CLK_DIVDR/q_int_Madd__add0000__and0000 <= (spi_intrface_SCK_GEN_CLK_DIVDR/qout(0) AND
spi_intrface_SCK_GEN_clk_cnt(1));
spi_intrface_SCK_GEN_CLK_DIVDR/q_int_Madd__add0000__and0001 <= (spi_intrface_SCK_GEN_clk_cnt(2) AND
spi_intrface_SCK_GEN_CLK_DIVDR/q_int_Madd__add0000__and0000);
spi_intrface_SCK_GEN_CLK_DIVDR/q_int_Madd__add0000__and0002 <= (spi_intrface_SCK_GEN_clk_cnt(3) AND
spi_intrface_SCK_GEN_CLK_DIVDR/q_int_Madd__add0000__and0001);
FDCPE_spi_intrface_SCK_GEN_CLK_DIVDR/qout0: FDCPE port map (spi_intrface_SCK_GEN_CLK_DIVDR/qout(0),NOT spi_intrface_SCK_GEN_CLK_DIVDR/qout(0),clk,spi_intrface_xmit_shift_reg__xor0001,'0','1');
spi_intrface_SCK_GEN_Mmux__mux0005_Result10 <= (NOT spi_intrface_SCK_GEN_sck_0 AND NOT uc_intrface_cpha);
spi_intrface_SCK_GEN_Mmux__mux0005_Result11 <= ((spi_intrface_SCK_GEN_Mmux__mux0005_Result7)
OR (spi_intrface_SCK_GEN_Mmux__mux0005_Result8));
spi_intrface_SCK_GEN_Mmux__mux0005_Result12 <= ((spi_intrface_SCK_GEN_Mmux__mux0005_Result9)
OR (spi_intrface_SCK_GEN_Mmux__mux0005_Result10));
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -