📄 spi_master.rpt
字号:
spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T37 3 3
spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T38 2 2
spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T39 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T4 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T40 1 3
spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T41 1 3
spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T42 2 2
spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T43 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T44 2 2
spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T45 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd4/Q/D 2 2
spi_intrface_spi_ctrl_sm_spi_state_Out41 1 2
spi_intrface_spi_ctrl_sm_spi_state_Out43 1 2
spi_intrface_spi_ctrl_sm_spi_state_Out44 1 2
spi_intrface_spi_ctrl_sm_spi_state_Out6 2 2
spi_intrface_spi_ctrl_sm_spi_state_Out7 1 2
Signal Total Total User
Name Pts Inps Assignment
spi_intrface_spi_ctrl_sm_spi_state_Out75 1 4
spi_intrface_spi_ctrl_sm_ss_in_int 4 4
spi_intrface_spi_ctrl_sm_ss_in_neg 3 3
spi_intrface_spi_ctrl_sm_ss_in_pos 3 3
spi_intrface_spi_ctrl_sm_xmit_load1 1 2
spi_intrface_spi_ctrl_sm_xmit_load4 1 2
spi_intrface_spi_ctrl_sm_xmit_load5 1 2
spi_intrface_spi_ctrl_sm_xmit_load6 1 3
spi_intrface_spi_ctrl_sm_xmit_load7 2 2
spi_intrface_xmit_load 1 2
spi_intrface_xmit_shift 1 2
spi_intrface_xmit_shift_reg__mux0000<0>1 1 2
spi_intrface_xmit_shift_reg__mux0000<1>3 1 2
spi_intrface_xmit_shift_reg__mux0000<1>1 1 2
spi_intrface_xmit_shift_reg__mux0000<2>3 1 2
spi_intrface_xmit_shift_reg__mux0000<2>1 1 2
spi_intrface_xmit_shift_reg__mux0000<3>1 1 2
spi_intrface_xmit_shift_reg__mux0000<3>3 1 2
spi_intrface_xmit_shift_reg__mux0000<4>1 1 2
spi_intrface_xmit_shift_reg__mux0000<4>3 1 2
spi_intrface_xmit_shift_reg__mux0000<5>3 1 2
spi_intrface_xmit_shift_reg__mux0000<5>1 1 2
spi_intrface_xmit_shift_reg__mux0000<6>3 1 2
spi_intrface_xmit_shift_reg__mux0000<6>1 1 2
spi_intrface_xmit_shift_reg__mux0000<7>3 1 2
spi_intrface_xmit_shift_reg__mux0000<7>1 1 2
spi_intrface_xmit_shift_reg__not0003 2 2
spi_intrface_xmit_shift_reg__xor0001 2 2
spi_intrface_xmit_shift_reg_data_int<0> 5 5
spi_intrface_xmit_shift_reg_data_int<1> 5 5
spi_intrface_xmit_shift_reg_data_int<2> 5 5
spi_intrface_xmit_shift_reg_data_int<3> 5 5
spi_intrface_xmit_shift_reg_data_int<4> 5 5
spi_intrface_xmit_shift_reg_data_int<5> 5 5
spi_intrface_xmit_shift_reg_data_int<6> 5 5
spi_intrface_xmit_shift_reg_data_int<7> 5 5
ss_n_int 2 2
uc_intrface_Mrom__mux0023__cmp_eq0000 1 2
uc_intrface_Mrom__mux0023__cmp_eq000010 1 3
uc_intrface_Mrom__mux0023__cmp_eq00008 1 2
Signal Total Total User
Name Pts Inps Assignment
uc_intrface_Mrom__mux0023__cmp_eq00009 1 4
uc_intrface_Mrom__mux0025__cmp_eq00001 1 2
uc_intrface_Mrom__mux0026__cmp_eq0000 1 4
uc_intrface_Mrom__mux0026__cmp_eq00005 1 4
uc_intrface_Mrom__mux0028__cmp_eq0000 1 4
uc_intrface_Mrom__mux0028__cmp_eq00006 1 4
uc_intrface_Mrom__mux0029__cmp_eq0000 1 2
uc_intrface_Mrom__mux0029__cmp_eq00007 1 2
uc_intrface_Mrom__mux0029__cmp_eq00008 1 4
uc_intrface_Mrom__mux0029__cmp_eq00009 1 3
uc_intrface_Mrom__mux0030__cmp_eq0000 1 2
uc_intrface_Mrom__mux0030__cmp_eq00007 1 2
uc_intrface_Mrom__mux0030__cmp_eq00008 1 4
uc_intrface_Mrom__mux0030__cmp_eq00009 1 3
uc_intrface__and0001 1 2
uc_intrface__and000110 1 8
uc_intrface__and000111 1 2
uc_intrface__cmp_ne0000 2 2
uc_intrface__mux0021<0>9 2 2
uc_intrface__mux0021<0>8 1 3
uc_intrface__mux0021<0>11 2 2
uc_intrface__mux0021<0>2 1 2
uc_intrface__mux0021<0>12 1 2
uc_intrface__mux0021<0>10 1 2
uc_intrface__mux0021<0>1 1 2
uc_intrface__mux0021<0>3 1 2
uc_intrface__mux0021<1>11 2 2
uc_intrface__mux0021<1>8 1 3
uc_intrface__mux0021<1>1 1 2
uc_intrface__mux0021<1>9 2 2
uc_intrface__mux0021<1>10 1 2
uc_intrface__mux0021<1>3 1 2
uc_intrface__mux0021<1>2 1 2
uc_intrface__mux0021<1>12 1 2
uc_intrface__mux0021<2>12 2 2
uc_intrface__mux0021<2>1 1 2
uc_intrface__mux0021<2>11 1 2
uc_intrface__mux0021<2>13 1 2
uc_intrface__mux0021<2>15 1 2
uc_intrface__mux0021<2>2 1 2
Signal Total Total User
Name Pts Inps Assignment
uc_intrface__mux0021<2>3 1 2
uc_intrface__mux0021<2>4 1 2
uc_intrface__mux0021<2>14 2 2
uc_intrface__mux0021<2>10 2 2
uc_intrface__mux0021<2>9 1 2
uc_intrface__mux0021<3>10 2 2
uc_intrface__mux0021<3>12 2 2
uc_intrface__mux0021<3>14 2 2
uc_intrface__mux0021<3>4 1 2
uc_intrface__mux0021<3>15 1 2
uc_intrface__mux0021<3>3 1 2
uc_intrface__mux0021<3>11 1 2
uc_intrface__mux0021<3>9 1 2
uc_intrface__mux0021<3>2 1 2
uc_intrface__mux0021<3>13 1 2
uc_intrface__mux0021<3>1 1 2
uc_intrface__mux0021<4>4 1 2
uc_intrface__mux0021<4>11 1 2
uc_intrface__mux0021<4>2 1 2
uc_intrface__mux0021<4>1 1 2
uc_intrface__mux0021<4>9 1 2
uc_intrface__mux0021<4>15 1 2
uc_intrface__mux0021<4>10 2 2
uc_intrface__mux0021<4>12 2 2
uc_intrface__mux0021<4>14 2 2
uc_intrface__mux0021<4>3 1 2
uc_intrface__mux0021<4>13 1 2
uc_intrface__mux0021<5>12 2 2
uc_intrface__mux0021<5>14 2 2
uc_intrface__mux0021<5>1 1 2
uc_intrface__mux0021<5>11 1 2
uc_intrface__mux0021<5>10 2 2
uc_intrface__mux0021<5>13 1 2
uc_intrface__mux0021<5>4 1 2
uc_intrface__mux0021<5>2 1 2
uc_intrface__mux0021<5>15 1 2
uc_intrface__mux0021<5>9 1 2
uc_intrface__mux0021<5>3 1 2
uc_intrface__mux0021<6>14 2 2
uc_intrface__mux0021<6>10 2 2
Signal Total Total User
Name Pts Inps Assignment
uc_intrface__mux0021<6>12 2 2
uc_intrface__mux0021<6>13 1 2
uc_intrface__mux0021<6>9 1 2
uc_intrface__mux0021<6>15 1 2
uc_intrface__mux0021<6>1 1 2
uc_intrface__mux0021<6>11 1 2
uc_intrface__mux0021<6>2 1 2
uc_intrface__mux0021<6>4 1 2
uc_intrface__mux0021<6>3 1 2
uc_intrface__mux0021<7>10 2 2
uc_intrface__mux0021<7>12 2 2
uc_intrface__mux0021<7>4 1 2
uc_intrface__mux0021<7>3 1 2
uc_intrface__mux0021<7>9 1 2
uc_intrface__mux0021<7>15 1 2
uc_intrface__mux0021<7>13 1 2
uc_intrface__mux0021<7>11 1 2
uc_intrface__mux0021<7>1 1 2
uc_intrface__mux0021<7>14 2 2
uc_intrface__mux0021<7>2 1 2
uc_intrface__not0014 1 3
uc_intrface__not0015 2 2
uc_intrface__not0016 1 3
uc_intrface__not0018 1 3
uc_intrface__not0019 3 3
uc_intrface__not00194 1 2
uc_intrface__not0020 3 3
uc_intrface__not00204 1 2
uc_intrface__not0021 2 2
uc_intrface__not00211 1 2
uc_intrface__not00213 2 2
uc_intrface__not00214 1 2
uc_intrface__not00215 2 2
uc_intrface__not00216 1 2
uc_intrface__not0022 3 3
uc_intrface__not00224 1 2
uc_intrface__or0000 3 3
uc_intrface__xor0012 2 2
uc_intrface__xor00121 2 2
uc_intrface__xor00127 1 5
Signal Total Total User
Name Pts Inps Assignment
uc_intrface_address_low<0> 3 3
uc_intrface_address_low<1> 3 3
uc_intrface_address_low<2> 3 3
uc_intrface_address_low<3> 3 3
uc_intrface_address_low<4> 3 3
uc_intrface_address_low<5> 3 3
uc_intrface_address_low<6> 3 3
uc_intrface_address_low<7> 3 3
uc_intrface_address_match 3 4
uc_intrface_bb 4 4
uc_intrface_clkdiv<0> 4 5
uc_intrface_clkdiv<1> 4 5
uc_intrface_cntrl_en 3 4
uc_intrface_cpha 4 5
uc_intrface_cpol 4 5
uc_intrface_data_in<6> 1 2
uc_intrface_data_oe 1 2
uc_intrface_data_oe1 1 2
uc_intrface_dt 3 4
uc_intrface_inten 4 5
uc_intrface_prs_state_FFd1 4 4
uc_intrface_prs_state_FFd1-In_T 2 2
uc_intrface_prs_state_FFd1-In_T1 1 2
uc_intrface_prs_state_FFd1-In_T10 1 2
uc_intrface_prs_state_FFd1-In_T5 1 2
uc_intrface_prs_state_FFd1-In_T7 2 2
uc_intrface_prs_state_FFd1-In_T8 1 2
uc_intrface_prs_state_FFd1-In_T9 1 2
uc_intrface_prs_state_FFd1/Q/D 2 2
uc_intrface_prs_state_FFd2 4 4
uc_intrface_prs_state_FFd2-In_T 2 2
uc_intrface_prs_state_FFd2-In_T5 1 4
uc_intrface_prs_state_FFd2-In_T6 1 2
uc_intrface_prs_state_FFd2-In_T7 1 3
uc_intrface_prs_state_FFd2-In_T8 2 2
uc_intrface_prs_state_FFd2-In_T9 1 2
uc_intrface_prs_state_FFd2/Q/D 2 2
uc_intrface_rcv_cpol 4 5
uc_intrface_rcv_en 3 5
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