📄 spi_master.rpt
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cpldfit: version I.31 Xilinx Inc.
No Fit Report
Design Name: spi_master Date: 11-26-2006, 12:26PM
Device Used: XC2C64A-5-PC44
Fitting Status: Design Rule Checking Failed
************************** Errors and Warnings ***************************
ERROR:Cpld:847 - Insufficient number of input pins. This design needs at least
16 but only 12 left after allocating other resources.
ERROR:Cpld:29 - Device XC2C64A-5-PC44 was disqualified.
ERROR:Cpld:30 - The design requires too many resources to fit in any of the
specified devices.
ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with
the selected implementation options.
************************* Mapped Resource Summary **************************
No logic has been mapped.
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
0 /64 ( 0%) 0 /224 ( 0%) 0 /160 ( 0%) 0 /64 ( 0%) 0 /33 ( 0%)
** Global Control Resources **
GCK GSR GTS
Used/Tot Used/Tot Used/Tot
0/3 0/1 0/4
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 16 0 | I/O : 0 25
Output : 12 0 | GCK/IO : 0 3
Bidirectional : 9 0 | GTS/IO : 0 4
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 37 0
End of Mapped Resource Summary
************************* Summary of UnMapped Logic ************************
** 21 Outputs **
Signal Total Total I/O User
Name Pts Inps STD Assignment
sck 5 5 LVCMOS18
rcv_full 4 4 LVCMOS18
ss_n<0> 5 5 LVCMOS18
ss_n<1> 5 5 LVCMOS18
ss_n<2> 5 5 LVCMOS18
ss_n<3> 5 5 LVCMOS18
ss_n<4> 5 5 LVCMOS18
ss_n<5> 5 5 LVCMOS18
ss_n<6> 5 5 LVCMOS18
ss_n<7> 5 5 LVCMOS18
xmit_empty 3 3 LVCMOS18
mosi 4 4 LVCMOS18
addr_data<0> 6 6 LVCMOS18
addr_data<1> 6 6 LVCMOS18
addr_data<2> 6 6 LVCMOS18
addr_data<3> 6 6 LVCMOS18
addr_data<4> 6 6 LVCMOS18
addr_data<5> 6 6 LVCMOS18
addr_data<6> 6 6 LVCMOS18
addr_data<7> 6 6 LVCMOS18
int_n 6 6 LVCMOS18
** 393 Buried Nodes **
Signal Total Total User
Name Pts Inps Assignment
rcv_data<0> 2 2
rcv_data<1> 5 5
rcv_data<2> 4 4
rcv_data<3> 4 4
rcv_data<4> 4 4
rcv_data<5> 4 4
rcv_data<6> 4 4
rcv_data<7> 4 4
rcv_load 1 2
spi_intrface_SCK_GEN_CLK_DIVDR/q_int_Madd__add0000__and0000 1 2
spi_intrface_SCK_GEN_CLK_DIVDR/q_int_Madd__add0000__and0001 1 2
spi_intrface_SCK_GEN_CLK_DIVDR/q_int_Madd__add0000__and0002 1 2
spi_intrface_SCK_GEN_CLK_DIVDR/qout<0> 3 3
spi_intrface_SCK_GEN_Mmux__mux0005_Result10 1 2
spi_intrface_SCK_GEN_Mmux__mux0005_Result11 2 2
spi_intrface_SCK_GEN_Mmux__mux0005_Result12 2 2
spi_intrface_SCK_GEN_Mmux__mux0005_Result13 1 2
spi_intrface_SCK_GEN_Mmux__mux0005_Result15 1 2
spi_intrface_SCK_GEN_Mmux__mux0005_Result7 1 2
spi_intrface_SCK_GEN_Mmux__mux0005_Result8 1 2
spi_intrface_SCK_GEN_Mmux__mux0005_Result9 1 2
spi_intrface_SCK_GEN_Mmux__mux0006_Result 1 2
spi_intrface_SCK_GEN_Mmux__mux0006_Result10 1 2
spi_intrface_SCK_GEN_Mmux__mux0006_Result2 1 2
spi_intrface_SCK_GEN_Mmux__mux0006_Result5 1 2
spi_intrface_SCK_GEN_Mmux__mux0006_Result6 1 2
spi_intrface_SCK_GEN_Mmux__mux0006_Result7 2 2
spi_intrface_SCK_GEN_Mmux__mux0006_Result8 2 2
spi_intrface_SCK_GEN_Mmux__mux0006_Result9 1 2
spi_intrface_SCK_GEN__mux000410 1 2
spi_intrface_SCK_GEN__mux000411 1 2
spi_intrface_SCK_GEN__mux000412 2 2
spi_intrface_SCK_GEN__mux000413 2 2
spi_intrface_SCK_GEN__mux000414 1 2
spi_intrface_SCK_GEN__mux000415 1 2
spi_intrface_SCK_GEN__mux000416 2 2
spi_intrface_SCK_GEN__mux00048 1 2
spi_intrface_SCK_GEN__mux00049 1 2
spi_intrface_SCK_GEN_clk_cnt<1> 4 4
spi_intrface_SCK_GEN_clk_cnt<2> 4 4
Signal Total Total User
Name Pts Inps Assignment
spi_intrface_SCK_GEN_clk_cnt<3> 4 4
spi_intrface_SCK_GEN_clk_cnt<4> 4 4
spi_intrface_SCK_GEN_sck_0 3 4
spi_intrface_SCK_GEN_sck_110 2 2
spi_intrface_SCK_GEN_sck_13 1 2
spi_intrface_SCK_GEN_sck_15 2 2
spi_intrface_SCK_GEN_sck_16 1 2
spi_intrface_SCK_GEN_sck_17 1 2
spi_intrface_SCK_GEN_sck_18 2 2
spi_intrface_SCK_GEN_sck_19 1 2
spi_intrface_SCK_GEN_sck_d1 3 3
spi_intrface_SCK_GEN_sck_int 4 4
spi_intrface_SCK_GEN_sck_int_d1 3 3
spi_intrface_clk0_mask 1 2
spi_intrface_rcv_shift_reg/_and0000 1 2
spi_intrface_rcv_shift_reg/_and000010 1 2
spi_intrface_rcv_shift_reg/_and000011 1 2
spi_intrface_rcv_shift_reg/_and000012 2 2
spi_intrface_rcv_shift_reg/_and000013 1 2
spi_intrface_rcv_shift_reg/_and000014 1 3
spi_intrface_rcv_shift_reg/_and000015 2 2
spi_intrface_rcv_shift_reg/_and00006 1 4
spi_intrface_rcv_shift_reg/_and00009 1 3
spi_intrface_rcv_shift_reg/_or0000 2 2
spi_intrface_rcv_shift_reg/_xor0000 2 2
spi_intrface_rcv_shift_reg/miso_neg 3 3
spi_intrface_rcv_shift_reg/miso_pos 3 3
spi_intrface_rcv_shift_reg/rcv_bitcnt_int<0> 3 3
spi_intrface_rcv_shift_reg/rcv_bitcnt_int<1> 4 4
spi_intrface_rcv_shift_reg/rcv_bitcnt_int<2> 4 4
spi_intrface_rcv_shift_reg/rcv_bitcnt_int_Madd__add0000__and0000 1 2
spi_intrface_rcv_shift_reg/shift_in1 1 2
spi_intrface_rcv_shift_reg/shift_in3 1 2
spi_intrface_sck_1 1 2
spi_intrface_sck_fe 1 2
spi_intrface_sck_re 1 2
spi_intrface_spi_ctrl_sm_BIT_CNTR/q_int_Madd__add0000__and0000 1 2
spi_intrface_spi_ctrl_sm_BIT_CNTR/q_int_Madd__add0000__and0001 1 2
spi_intrface_spi_ctrl_sm__not0003 2 2
spi_intrface_spi_ctrl_sm__xor0004 2 2
Signal Total Total User
Name Pts Inps Assignment
spi_intrface_spi_ctrl_sm__xor00041 1 2
spi_intrface_spi_ctrl_sm__xor00045 1 2
spi_intrface_spi_ctrl_sm__xor00046 1 3
spi_intrface_spi_ctrl_sm__xor0008 2 2
spi_intrface_spi_ctrl_sm_bit_cnt<0> 4 4
spi_intrface_spi_ctrl_sm_bit_cnt<1> 5 5
spi_intrface_spi_ctrl_sm_bit_cnt<2> 5 5
spi_intrface_spi_ctrl_sm_bit_cnt<3> 5 5
spi_intrface_spi_ctrl_sm_bit_cnt_reset 1 2
spi_intrface_spi_ctrl_sm_bit_cnt_rst 2 2
spi_intrface_spi_ctrl_sm_clk0_mask 1 2
spi_intrface_spi_ctrl_sm_clk0_mask10 2 2
spi_intrface_spi_ctrl_sm_clk0_mask6 1 2
spi_intrface_spi_ctrl_sm_clk0_mask7 1 2
spi_intrface_spi_ctrl_sm_clk0_mask8 2 2
spi_intrface_spi_ctrl_sm_clk0_mask9 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd1 4 4
spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T1 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T4 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T6 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T7 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T8 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T9 2 2
spi_intrface_spi_ctrl_sm_spi_state_FFd1/Q/D 2 2
spi_intrface_spi_ctrl_sm_spi_state_FFd2 4 4
spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T1 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T3 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T5 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T6 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T7 2 2
spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T8 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T9 2 2
spi_intrface_spi_ctrl_sm_spi_state_FFd2/Q/D 2 2
spi_intrface_spi_ctrl_sm_spi_state_FFd3 4 4
spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T 2 2
spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T1 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T11 1 3
spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T12 1 2
Signal Total Total User
Name Pts Inps Assignment
spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T13 1 3
spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T14 2 2
spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T15 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T16 1 3
spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T17 2 2
spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T18 1 3
spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T5 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T8 2 2
spi_intrface_spi_ctrl_sm_spi_state_FFd3/Q/D 2 2
spi_intrface_spi_ctrl_sm_spi_state_FFd4 4 4
spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T 3 3
spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T14 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T2 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T20 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T27 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T28 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T29 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T30 1 3
spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T31 1 6
spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T32 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T33 1 4
spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T34 1 2
spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T35 1 4
spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T36 3 3
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