spi_master.syr

spi总线的vhdl代码

Synthesizing Unit <upcnt5>.
    Related source file is "H:/file/ip/IP_SPI/upcnt5.vhd".
    Found 5-bit up counter for signal <q_int>.
    Summary:
	inferred   1 Counter(s).
Unit <upcnt5> synthesized.


Synthesizing Unit <upcnt4>.
    Related source file is "H:/file/ip/IP_SPI/upcnt4.vhd".
    Found 4-bit up counter for signal <q_int>.
    Summary:
	inferred   1 Counter(s).
Unit <upcnt4> synthesized.


Synthesizing Unit <sck_logic>.
    Related source file is "H:/file/ip/IP_SPI/sck_logic.vhd".
WARNING:Xst:646 - Signal <clk_cnt<0>> is assigned but never used.
    Found 1-bit tristate buffer for signal <sck>.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0005> created at line 190.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0006> created at line 118.
    Found 1-bit register for signal <sck_0>.
    Found 1-bit register for signal <sck_d1>.
    Found 1-bit register for signal <sck_int>.
    Found 1-bit register for signal <sck_int_d1>.
    Found 1-bit register for signal <sck_out>.
    Summary:
	inferred   5 D-type flip-flop(s).
	inferred   1 Tristate(s).
Unit <sck_logic> synthesized.


Synthesizing Unit <spi_control_sm>.
    Related source file is "H:/file/ip/IP_SPI/spi_control_sm.vhd".
    Found finite state machine <FSM_1> for signal <spi_state>.
    -----------------------------------------------------------------------
    | States             | 11                                             |
    | Transitions        | 33                                             |
    | Inputs             | 9                                              |
    | Outputs            | 8                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | $or0000 (positive)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <rcv_full>.
    Found 1-bit register for signal <xmit_empty>.
    Found 8-bit tristate buffer for signal <ss_n>.
    Found 1-bit register for signal <ss_in_int>.
    Found 1-bit register for signal <ss_in_neg>.
    Found 1-bit register for signal <ss_in_pos>.
    Found 8-bit register for signal <ss_n_out>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  13 D-type flip-flop(s).
	inferred   8 Tristate(s).
Unit <spi_control_sm> synthesized.


Synthesizing Unit <spi_interface>.
    Related source file is "H:/file/ip/IP_SPI/spi_interface.vhd".
Unit <spi_interface> synthesized.


Synthesizing Unit <spi_master>.
    Related source file is "H:/file/ip/IP_SPI/spi_master.vhd".
Unit <spi_master> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 6
 4x1-bit ROM                                           : 6
# Counters                                             : 3
 3-bit up counter                                      : 1
 4-bit up counter                                      : 1
 5-bit up counter                                      : 1
# Registers                                            : 48
 1-bit register                                        : 40
 2-bit register                                        : 1
 8-bit register                                        : 7
# Multiplexers                                         : 2
 1-bit 4-to-1 multiplexer                              : 2
# Tristates                                            : 4
 1-bit tristate buffer                                 : 2
 8-bit tristate buffer                                 : 2

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_1> for best encoding.
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_1> on signal <spi_state[1:4]> with sequential encoding.
-------------------------
 State       | Encoding
-------------------------
 idle        | 0000
 assert_ssn1 | 0001
 assert_ssn2 | 0010
 unmask_sck  | 0011
 xfer_bit    | 0100
 assert_done | 0101
 chk_start   | 0110
 mask_sck    | 0111
 hold_ssn1   | 1000
 hold_ssn2   | 1001
 negate_ssn  | 1010
-------------------------
Optimizing FSM <FSM_0> on signal <prs_state[1:2]> with gray encoding.
-------------------------
 State       | Encoding
-------------------------
 idle        | 00
 addr_decode | 01
 data_trs    | 11
 end_cycle   | 10
-------------------------
WARNING:Xst:1291 - FF/Latch <7> is unconnected in block <data_int>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 6
 4x1-bit ROM                                           : 6
# Counters                                             : 3
 3-bit up counter                                      : 1
 4-bit up counter                                      : 1
 5-bit up counter                                      : 1
# Registers                                            : 78
 Flip-Flops                                            : 78
# Multiplexers                                         : 2
 1-bit 4-to-1 multiplexer                              : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <data_int_7> is unconnected in block <spi_rcv_shift_reg>.
WARNING:Xst:1348 - Unit sck_logic is merged (output interface has tristates)
WARNING:Xst:1348 - Unit spi_interface is merged (output interface has tristates)
WARNING:Xst:1348 - Unit spi_xmit_shift_reg is merged (output interface has tristates)
WARNING:Xst:1348 - Unit uc_interface is merged (output interface has tristates)
WARNING:Xst:1348 - Unit spi_control_sm is merged (output interface has tristates)

Optimizing unit <spi_master> ...
  implementation constraint: INIT=r	 : uc_intrface_prs_state_FFd2
  implementation constraint: INIT=r	 : uc_intrface_prs_state_FFd1
  implementation constraint: INIT=r	 : spi_intrface_spi_ctrl_sm_spi_state_FFd3
  implementation constraint: INIT=r	 : spi_intrface_spi_ctrl_sm_spi_state_FFd4
  implementation constraint: INIT=r	 : spi_intrface_spi_ctrl_sm_spi_state_FFd1
  implementation constraint: INIT=r	 : spi_intrface_spi_ctrl_sm_spi_state_FFd2

Optimizing unit <spi_rcv_shift_reg> ...

Optimizing unit <upcnt5> ...

Optimizing unit <upcnt4> ...

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : spi_master.ngr
Top Level Output File Name         : spi_master
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : YES
Target Technology                  : CoolRunner2 CPLDs
Macro Preserve                     : YES
XOR Preserve                       : YES
Clock Enable                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 37

Cell Usage :
# BELS                             : 593
#      AND2                        : 203
#      AND3                        : 22
#      AND4                        : 12
#      AND5                        : 1
#      AND6                        : 1
#      AND8                        : 1
#      INV                         : 239
#      OR2                         : 97
#      OR3                         : 7
#      VCC                         : 1
#      XOR2                        : 9
# FlipFlops/Latches                : 115
#      FDC                         : 32
#      FDCE                        : 65
#      FDP                         : 11
#      FDPE                        : 1
#      FTC                         : 6
# IO Buffers                       : 37
#      IBUF                        : 16
#      IOBUFE                      : 9
#      OBUF                        : 3
#      OBUFE                       : 9
# Others                           : 1
#      NAND2B1                     : 1
=========================================================================
CPU : 20.80 / 23.55 s | Elapsed : 21.00 / 23.00 s
 
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Total memory usage is 123028 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   11 (   0 filtered)
Number of infos    :    5 (   0 filtered)