spi_master.syr

spi总线的vhdl代码

Release  - xst I.31
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 2.70 s | Elapsed : 0.00 / 2.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 2.70 s | Elapsed : 0.00 / 2.00 s
 
--> Reading design: spi_master.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "spi_master.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "spi_master"
Output Format                      : NGC
Target Device                      : CoolRunner2 CPLDs

---- Source Options
Top Module Name                    : spi_master
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain

---- Other Options
lso                                : spi_master.lso
verilog2001                        : YES
safe_implementation                : No
Clock Enable                       : YES
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "H:/file/ip/IP_SPI/upcnt4.vhd" in Library work.
Architecture definition of Entity upcnt4 is up to date.
Compiling vhdl file "H:/file/ip/IP_SPI/upcnt5.vhd" in Library work.
Architecture definition of Entity upcnt5 is up to date.
Compiling vhdl file "H:/file/ip/IP_SPI/sck_logic.vhd" in Library work.
Architecture definition of Entity sck_logic is up to date.
Compiling vhdl file "H:/file/ip/IP_SPI/spi_control_sm.vhd" in Library work.
Architecture definition of Entity spi_control_sm is up to date.
Compiling vhdl file "H:/file/ip/IP_SPI/spi_rcv_shift_reg.vhd" in Library work.
Architecture definition of Entity spi_rcv_shift_reg is up to date.
Compiling vhdl file "H:/file/ip/IP_SPI/spi_xmit_shift_reg.vhd" in Library work.
Architecture definition of Entity spi_xmit_shift_reg is up to date.
Compiling vhdl file "H:/file/ip/IP_SPI/spi_interface.vhd" in Library work.
Architecture schematic of Entity spi_interface is up to date.
Compiling vhdl file "H:/file/ip/IP_SPI/uc_interface.vhd" in Library work.
Architecture behaviour of Entity uc_interface is up to date.
Compiling vhdl file "H:/file/ip/IP_SPI/spi_master.vhd" in Library work.
Architecture schematic of Entity spi_master is up to date.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <spi_master> in library <work> (architecture <schematic>).

Analyzing hierarchy for entity <spi_interface> in library <work> (architecture <schematic>).

Analyzing hierarchy for entity <uc_interface> in library <work> (architecture <behaviour>) with generics.
	UC_ADDRESS = "00000000"

Analyzing hierarchy for entity <sck_logic> in library <work> (architecture <definition>).

Analyzing hierarchy for entity <spi_control_sm> in library <work> (architecture <definition>).

Analyzing hierarchy for entity <spi_rcv_shift_reg> in library <work> (architecture <definition>).

Analyzing hierarchy for entity <spi_xmit_shift_reg> in library <work> (architecture <definition>).

Analyzing hierarchy for entity <upcnt5> in library <work> (architecture <definition>).

Analyzing hierarchy for entity <upcnt4> in library <work> (architecture <definition>).

Building hierarchy successfully finished.
INFO:Xst:2555 - '-hierarchy_separator' switch is being deprecated in a future release.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <spi_master> in library <work> (Architecture <schematic>).
Entity <spi_master> analyzed. Unit <spi_master> generated.

Analyzing Entity <spi_interface> in library <work> (Architecture <schematic>).
WARNING:Xst:37 - Unknown property "fpga_dont_touch".
Entity <spi_interface> analyzed. Unit <spi_interface> generated.

Analyzing Entity <sck_logic> in library <work> (Architecture <definition>).
INFO:Xst:1561 - "H:/file/ip/IP_SPI/sck_logic.vhd" line 126: Mux is complete : default of case is discarded
INFO:Xst:1561 - "H:/file/ip/IP_SPI/sck_logic.vhd" line 173: Mux is complete : default of case is discarded
INFO:Xst:1561 - "H:/file/ip/IP_SPI/sck_logic.vhd" line 202: Mux is complete : default of case is discarded
Entity <sck_logic> analyzed. Unit <sck_logic> generated.

Analyzing Entity <upcnt5> in library <work> (Architecture <definition>).
Entity <upcnt5> analyzed. Unit <upcnt5> generated.

Analyzing Entity <spi_control_sm> in library <work> (Architecture <definition>).
Entity <spi_control_sm> analyzed. Unit <spi_control_sm> generated.

Analyzing Entity <upcnt4> in library <work> (Architecture <definition>).
Entity <upcnt4> analyzed. Unit <upcnt4> generated.

Analyzing Entity <spi_rcv_shift_reg> in library <work> (Architecture <definition>).
Entity <spi_rcv_shift_reg> analyzed. Unit <spi_rcv_shift_reg> generated.

Analyzing Entity <spi_xmit_shift_reg> in library <work> (Architecture <definition>).
Entity <spi_xmit_shift_reg> analyzed. Unit <spi_xmit_shift_reg> generated.

Analyzing generic Entity <uc_interface> in library <work> (Architecture <behaviour>).
	UC_ADDRESS = "00000000"
INFO:Xst:1304 - Contents of register <int_reset> in unit <uc_interface> never changes during circuit operation. The register is replaced by logic.
Entity <uc_interface> analyzed. Unit <uc_interface> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <uc_interface>.
    Related source file is "H:/file/ip/IP_SPI/uc_interface.vhd".
WARNING:Xst:646 - Signal <int_reset> is assigned but never used.
    Found finite state machine <FSM_0> for signal <prs_state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 12                                             |
    | Inputs             | 5                                              |
    | Outputs            | 5                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 4x1-bit ROM for signal <$mux0023>.
    Found 4x1-bit ROM for signal <$mux0025>.
    Found 4x1-bit ROM for signal <$mux0026>.
    Found 4x1-bit ROM for signal <$mux0028>.
    Found 4x1-bit ROM for signal <$mux0029>.
    Found 4x1-bit ROM for signal <$mux0030>.
    Found 8-bit tristate buffer for signal <addr_data>.
    Found 1-bit register for signal <start>.
    Found 1-bit register for signal <cpol>.
    Found 1-bit register for signal <rcv_full_reset>.
    Found 1-bit register for signal <spien>.
    Found 1-bit register for signal <xmit_empty_reset>.
    Found 1-bit register for signal <rcv_cpol>.
    Found 8-bit register for signal <spissr>.
    Found 8-bit register for signal <spitr>.
    Found 1-bit register for signal <int_n>.
    Found 2-bit register for signal <clkdiv>.
    Found 1-bit register for signal <cpha>.
    Found 8-bit register for signal <address_low>.
    Found 1-bit register for signal <address_match>.
    Found 1-bit register for signal <bb>.
    Found 1-bit register for signal <cntrl_en>.
    Found 8-bit register for signal <data_out>.
    Found 1-bit register for signal <dt>.
    Found 1-bit register for signal <inten>.
    Found 1-bit register for signal <rcv_en>.
    Found 1-bit register for signal <spierr>.
    Found 1-bit register for signal <spierr_reset>.
    Found 8-bit register for signal <spirr>.
    Found 1-bit register for signal <ssel_en>.
    Found 1-bit register for signal <stat_en>.
    Found 1-bit register for signal <xmit_en>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   6 ROM(s).
	inferred  19 D-type flip-flop(s).
	inferred   8 Tristate(s).
Unit <uc_interface> synthesized.


Synthesizing Unit <spi_rcv_shift_reg>.
    Related source file is "H:/file/ip/IP_SPI/spi_rcv_shift_reg.vhd".
WARNING:Xst:646 - Signal <data_int<7>> is assigned but never used.
    Found 8-bit register for signal <data_int>.
    Found 1-bit register for signal <miso_neg>.
    Found 1-bit register for signal <miso_pos>.
    Found 3-bit up counter for signal <rcv_bitcnt_int>.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
Unit <spi_rcv_shift_reg> synthesized.


Synthesizing Unit <spi_xmit_shift_reg>.
    Related source file is "H:/file/ip/IP_SPI/spi_xmit_shift_reg.vhd".
    Found 1-bit tristate buffer for signal <mosi>.
    Found 8-bit register for signal <data_int>.
    Found 1-bit register for signal <mosi_int>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   1 Tristate(s).
Unit <spi_xmit_shift_reg> synthesized.