spi_master.xml

spi总线的vhdl代码

<document><ascFile>spi_master.rpt</ascFile><devFile>D:/softs/Xilinx/xbr/data/xc2c64a.chp</devFile><mfdFile>spi_master.mfd</mfdFile><htmlFile logo="coolrunnerII_logo.jpg" pin_legend="pinlegend.htm" logic_legend="logiclegend.htm"/><header pkg="PC44" date="11-26-2006" time=" 12:26PM" speed="-5" design="spi_master" device="XC2C64A" status="10" eqnType="1" version="1.0" statusStr="Design Rule Checking Failed" swVersion="I.31"/><inputs id="sckPIN_SPECSIG"/><inputs id="addr_data7PIN_SPECSIG"/><inputs id="addr_data6PIN_SPECSIG"/><inputs id="addr_data5PIN_SPECSIG"/><inputs id="addr_data4PIN_SPECSIG"/><inputs id="addr_data3PIN_SPECSIG"/><inputs id="addr_data2PIN_SPECSIG"/><inputs id="addr_data1PIN_SPECSIG"/><inputs id="addr_data0PIN_SPECSIG"/><inputs id="clk"/><inputs id="reset"/><inputs id="wr_n"/><inputs id="ale_n"/><inputs id="rd_n"/><inputs id="miso"/><inputs id="psen_n"/><inputs id="ss_in_n"/><inputs id="addr0_SPECSIG"/><inputs id="addr1_SPECSIG"/><inputs id="addr2_SPECSIG"/><inputs id="addr3_SPECSIG"/><inputs id="addr4_SPECSIG"/><inputs id="addr5_SPECSIG"/><inputs id="addr6_SPECSIG"/><inputs id="addr7_SPECSIG"/><pin id="FB_PIN41" use="VCCAUX" pinnum="41"/><pin id="FB_PIN13" use="VCCIO-UNUSED" pinnum="13"/><pin id="FB_PIN21" use="VCC" pinnum="21"/><pin id="FB_PIN32" use="VCCIO-UNUSED" pinnum="32"/><failuretable><failsig name="rcv_data0_SPECSIG"/><failsig name="rcv_data1_SPECSIG"/><failsig name="rcv_data2_SPECSIG"/><failsig name="rcv_data3_SPECSIG"/><failsig name="rcv_data4_SPECSIG"/><failsig name="rcv_data5_SPECSIG"/><failsig name="rcv_data6_SPECSIG"/><failsig name="rcv_data7_SPECSIG"/><failsig name="rcv_load"/><failsig name="spi_intrface_SCK_GEN_CLK_DIVDRq_int_Madd__add0000__and0000_SPECSIG"/><failsig name="spi_intrface_SCK_GEN_CLK_DIVDRq_int_Madd__add0000__and0001_SPECSIG"/><failsig name="spi_intrface_SCK_GEN_CLK_DIVDRq_int_Madd__add0000__and0002_SPECSIG"/><failsig name="spi_intrface_SCK_GEN_CLK_DIVDRqout0_SPECSIG"/><failsig name="spi_intrface_SCK_GEN_Mmux__mux0005_Result10"/><failsig name="spi_intrface_SCK_GEN_Mmux__mux0005_Result11"/><failsig name="spi_intrface_SCK_GEN_Mmux__mux0005_Result12"/><failsig name="spi_intrface_SCK_GEN_Mmux__mux0005_Result13"/><failsig name="spi_intrface_SCK_GEN_Mmux__mux0005_Result15"/><failsig name="spi_intrface_SCK_GEN_Mmux__mux0005_Result7"/><failsig name="spi_intrface_SCK_GEN_Mmux__mux0005_Result8"/><failsig name="spi_intrface_SCK_GEN_Mmux__mux0005_Result9"/><failsig name="spi_intrface_SCK_GEN_Mmux__mux0006_Result"/><failsig name="spi_intrface_SCK_GEN_Mmux__mux0006_Result10"/><failsig name="spi_intrface_SCK_GEN_Mmux__mux0006_Result2"/><failsig name="spi_intrface_SCK_GEN_Mmux__mux0006_Result5"/><failsig name="spi_intrface_SCK_GEN_Mmux__mux0006_Result6"/><failsig name="spi_intrface_SCK_GEN_Mmux__mux0006_Result7"/><failsig name="spi_intrface_SCK_GEN_Mmux__mux0006_Result8"/><failsig name="spi_intrface_SCK_GEN_Mmux__mux0006_Result9"/><failsig name="spi_intrface_SCK_GEN__mux000410"/><failsig name="spi_intrface_SCK_GEN__mux000411"/><failsig name="spi_intrface_SCK_GEN__mux000412"/><failsig name="spi_intrface_SCK_GEN__mux000413"/><failsig name="spi_intrface_SCK_GEN__mux000414"/><failsig name="spi_intrface_SCK_GEN__mux000415"/><failsig name="spi_intrface_SCK_GEN__mux000416"/><failsig name="spi_intrface_SCK_GEN__mux00048"/><failsig name="spi_intrface_SCK_GEN__mux00049"/><failsig name="spi_intrface_SCK_GEN_clk_cnt1_SPECSIG"/><failsig name="spi_intrface_SCK_GEN_clk_cnt2_SPECSIG"/><failsig name="spi_intrface_SCK_GEN_clk_cnt3_SPECSIG"/><failsig name="spi_intrface_SCK_GEN_clk_cnt4_SPECSIG"/><failsig name="spi_intrface_SCK_GEN_sck_0"/><failsig name="spi_intrface_SCK_GEN_sck_110"/><failsig name="spi_intrface_SCK_GEN_sck_13"/><failsig name="spi_intrface_SCK_GEN_sck_15"/><failsig name="spi_intrface_SCK_GEN_sck_16"/><failsig name="spi_intrface_SCK_GEN_sck_17"/><failsig name="spi_intrface_SCK_GEN_sck_18"/><failsig name="spi_intrface_SCK_GEN_sck_19"/><failsig name="spi_intrface_SCK_GEN_sck_d1"/><failsig name="spi_intrface_SCK_GEN_sck_int"/><failsig name="spi_intrface_SCK_GEN_sck_int_d1"/><failsig name="spi_intrface_SCK_GEN_sck_out"/><failsig name="spi_intrface_clk0_mask"/><failsig name="spi_intrface_rcv_shift_reg_and0000_SPECSIG"/><failsig name="spi_intrface_rcv_shift_reg_and000010_SPECSIG"/><failsig name="spi_intrface_rcv_shift_reg_and000011_SPECSIG"/><failsig name="spi_intrface_rcv_shift_reg_and000012_SPECSIG"/><failsig name="spi_intrface_rcv_shift_reg_and000013_SPECSIG"/><failsig name="spi_intrface_rcv_shift_reg_and000014_SPECSIG"/><failsig name="spi_intrface_rcv_shift_reg_and000015_SPECSIG"/><failsig name="spi_intrface_rcv_shift_reg_and00006_SPECSIG"/><failsig name="spi_intrface_rcv_shift_reg_and00009_SPECSIG"/><failsig name="spi_intrface_rcv_shift_reg_or0000_SPECSIG"/><failsig name="spi_intrface_rcv_shift_reg_xor0000_SPECSIG"/><failsig name="spi_intrface_rcv_shift_regmiso_neg_SPECSIG"/><failsig name="spi_intrface_rcv_shift_regmiso_pos_SPECSIG"/><failsig name="spi_intrface_rcv_shift_regrcv_bitcnt_int0_SPECSIG"/><failsig name="spi_intrface_rcv_shift_regrcv_bitcnt_int1_SPECSIG"/><failsig name="spi_intrface_rcv_shift_regrcv_bitcnt_int2_SPECSIG"/><failsig name="spi_intrface_rcv_shift_regrcv_bitcnt_int_Madd__add0000__and0000_SPECSIG"/><failsig name="spi_intrface_rcv_shift_regshift_in1_SPECSIG"/><failsig name="spi_intrface_rcv_shift_regshift_in3_SPECSIG"/><failsig name="spi_intrface_sck_1"/><failsig name="spi_intrface_sck_fe"/><failsig name="spi_intrface_sck_re"/><failsig name="spi_intrface_spi_ctrl_sm_BIT_CNTRq_int_Madd__add0000__and0000_SPECSIG"/><failsig name="spi_intrface_spi_ctrl_sm_BIT_CNTRq_int_Madd__add0000__and0001_SPECSIG"/><failsig name="spi_intrface_spi_ctrl_sm__not0003"/><failsig name="spi_intrface_spi_ctrl_sm__xor0004"/><failsig name="spi_intrface_spi_ctrl_sm__xor00041"/><failsig name="spi_intrface_spi_ctrl_sm__xor00045"/><failsig name="spi_intrface_spi_ctrl_sm__xor00046"/><failsig name="spi_intrface_spi_ctrl_sm__xor0008"/><failsig name="spi_intrface_spi_ctrl_sm_bit_cnt0_SPECSIG"/><failsig name="spi_intrface_spi_ctrl_sm_bit_cnt1_SPECSIG"/><failsig name="spi_intrface_spi_ctrl_sm_bit_cnt2_SPECSIG"/><failsig name="spi_intrface_spi_ctrl_sm_bit_cnt3_SPECSIG"/><failsig name="spi_intrface_spi_ctrl_sm_bit_cnt_reset"/><failsig name="spi_intrface_spi_ctrl_sm_bit_cnt_rst"/><failsig name="spi_intrface_spi_ctrl_sm_clk0_mask"/><failsig name="spi_intrface_spi_ctrl_sm_clk0_mask10"/><failsig name="spi_intrface_spi_ctrl_sm_clk0_mask6"/><failsig name="spi_intrface_spi_ctrl_sm_clk0_mask7"/><failsig name="spi_intrface_spi_ctrl_sm_clk0_mask8"/><failsig name="spi_intrface_spi_ctrl_sm_clk0_mask9"/><failsig name="spi_intrface_spi_ctrl_sm_rcv_full"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd1"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T1"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T4"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T6"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T7"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T8"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd1-In_T9"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd1QD_SPECSIG"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd2"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T1"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T3"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T5"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T6"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T7"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T8"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd2-In_T9"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd2QD_SPECSIG"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd3"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T1"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T11"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T12"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T13"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T14"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T15"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T16"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T17"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T18"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T5"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd3-In_T8"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd3QD_SPECSIG"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T14"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T2"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T20"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T27"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T28"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T29"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T30"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T31"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T32"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T33"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T34"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T35"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T36"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T37"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T38"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T39"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T4"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T40"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T41"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T42"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T43"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T44"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T45"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_FFd4QD_SPECSIG"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_Out41"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_Out43"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_Out44"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_Out6"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_Out7"/><failsig name="spi_intrface_spi_ctrl_sm_spi_state_Out75"/><failsig name="spi_intrface_spi_ctrl_sm_ss_in_int"/><failsig name="spi_intrface_spi_ctrl_sm_ss_in_neg"/><failsig name="spi_intrface_spi_ctrl_sm_ss_in_pos"/><failsig name="spi_intrface_spi_ctrl_sm_ss_n_out0_SPECSIG"/><failsig name="spi_intrface_spi_ctrl_sm_ss_n_out1_SPECSIG"/><failsig name="spi_intrface_spi_ctrl_sm_ss_n_out2_SPECSIG"/><failsig name="spi_intrface_spi_ctrl_sm_ss_n_out3_SPECSIG"/><failsig name="spi_intrface_spi_ctrl_sm_ss_n_out4_SPECSIG"/><failsig name="spi_intrface_spi_ctrl_sm_ss_n_out5_SPECSIG"/><failsig name="spi_intrface_spi_ctrl_sm_ss_n_out6_SPECSIG"/><failsig name="spi_intrface_spi_ctrl_sm_ss_n_out7_SPECSIG"/><failsig name="spi_intrface_spi_ctrl_sm_xmit_empty"/><failsig name="spi_intrface_spi_ctrl_sm_xmit_load1"/><failsig name="spi_intrface_spi_ctrl_sm_xmit_load4"/><failsig name="spi_intrface_spi_ctrl_sm_xmit_load5"/><failsig name="spi_intrface_spi_ctrl_sm_xmit_load6"/><failsig name="spi_intrface_spi_ctrl_sm_xmit_load7"/><failsig name="spi_intrface_xmit_load"/><failsig name="spi_intrface_xmit_shift"/><failsig name="spi_intrface_xmit_shift_reg__mux000001_SPECSIG"/><failsig name="spi_intrface_xmit_shift_reg__mux000013_SPECSIG"/><failsig name="spi_intrface_xmit_shift_reg__mux000011_SPECSIG"/><failsig name="spi_intrface_xmit_shift_reg__mux000023_SPECSIG"/><failsig name="spi_intrface_xmit_shift_reg__mux000021_SPECSIG"/><failsig name="spi_intrface_xmit_shift_reg__mux000031_SPECSIG"/><failsig name="spi_intrface_xmit_shift_reg__mux000033_SPECSIG"/><failsig name="spi_intrface_xmit_shift_reg__mux000041_SPECSIG"/><failsig name="spi_intrface_xmit_shift_reg__mux000043_SPECSIG"/><failsig name="spi_intrface_xmit_shift_reg__mux000053_SPECSIG"/><failsig name="spi_intrface_xmit_shift_reg__mux000051_SPECSIG"/><failsig name="spi_intrface_xmit_shift_reg__mux000063_SPECSIG"/><failsig name="spi_intrface_xmit_shift_reg__mux000061_SPECSIG"/><failsig name="spi_intrface_xmit_shift_reg__mux000073_SPECSIG"/><failsig name="spi_intrface_xmit_shift_reg__mux000071_SPECSIG"/><failsig name="spi_intrface_xmit_shift_reg__not0003"/><failsig name="spi_intrface_xmit_shift_reg__xor0001"/><failsig name="spi_intrface_xmit_shift_reg_data_int0_SPECSIG"/><failsig name="spi_intrface_xmit_shift_reg_data_int1_SPECSIG"/><failsig name="spi_intrface_xmit_shift_reg_data_int2_SPECSIG"/><failsig name="spi_intrface_xmit_shift_reg_data_int3_SPECSIG"/><failsig name="spi_intrface_xmit_shift_reg_data_int4_SPECSIG"/><failsig name="spi_intrface_xmit_shift_reg_data_int5_SPECSIG"/><failsig name="spi_intrface_xmit_shift_reg_data_int6_SPECSIG"/><failsig name="spi_intrface_xmit_shift_reg_data_int7_SPECSIG"/><failsig name="spi_intrface_xmit_shift_reg_mosi_int"/><failsig name="ss_n_int"/><failsig name="uc_intrface_Mrom__mux0023__cmp_eq0000"/><failsig name="uc_intrface_Mrom__mux0023__cmp_eq000010"/><failsig name="uc_intrface_Mrom__mux0023__cmp_eq00008"/><failsig name="uc_intrface_Mrom__mux0023__cmp_eq00009"/><failsig name="uc_intrface_Mrom__mux0025__cmp_eq00001"/><failsig name="uc_intrface_Mrom__mux0026__cmp_eq0000"/><failsig name="uc_intrface_Mrom__mux0026__cmp_eq00005"/><failsig name="uc_intrface_Mrom__mux0028__cmp_eq0000"/><failsig name="uc_intrface_Mrom__mux0028__cmp_eq00006"/><failsig name="uc_intrface_Mrom__mux0029__cmp_eq0000"/><failsig name="uc_intrface_Mrom__mux0029__cmp_eq00007"/><failsig name="uc_intrface_Mrom__mux0029__cmp_eq00008"/><failsig name="uc_intrface_Mrom__mux0029__cmp_eq00009"/><failsig name="uc_intrface_Mrom__mux0030__cmp_eq0000"/><failsig name="uc_intrface_Mrom__mux0030__cmp_eq00007"/><failsig name="uc_intrface_Mrom__mux0030__cmp_eq00008"/><failsig name="uc_intrface_Mrom__mux0030__cmp_eq00009"/><failsig name="uc_intrface__and0001"/><failsig name="uc_intrface__and000110"/><failsig name="uc_intrface__and000111"/><failsig name="uc_intrface__cmp_ne0000"/><failsig name="uc_intrface__mux002109_SPECSIG"/><failsig name="uc_intrface__mux002108_SPECSIG"/><failsig name="uc_intrface__mux0021011_SPECSIG"/><failsig name="uc_intrface__mux002102_SPECSIG"/><failsig name="uc_intrface__mux0021012_SPECSIG"/><failsig name="uc_intrface__mux0021010_SPECSIG"/><failsig name="uc_intrface__mux002101_SPECSIG"/><failsig name="uc_intrface__mux002103_SPECSIG"/><failsig name="uc_intrface__mux0021111_SPECSIG"/><failsig name="uc_intrface__mux002118_SPECSIG"/><failsig name="uc_intrface__mux002111_SPECSIG"/><failsig name="uc_intrface__mux002119_SPECSIG"/><failsig name="uc_intrface__mux0021110_SPECSIG"/><failsig name="uc_intrface__mux002113_SPECSIG"/><failsig name="uc_intrface__mux002112_SPECSIG"/><failsig name="uc_intrface__mux0021112_SPECSIG"/><failsig name="uc_intrface__mux0021212_SPECSIG"/><failsig name="uc_intrface__mux002121_SPECSIG"/><failsig name="uc_intrface__mux0021211_SPECSIG"/><failsig name="uc_intrface__mux0021213_SPECSIG"/><failsig name="uc_intrface__mux0021215_SPECSIG"/><failsig name="uc_intrface__mux002122_SPECSIG"/><failsig name="uc_intrface__mux002123_SPECSIG"/><failsig name="uc_intrface__mux002124_SPECSIG"/><failsig name="uc_intrface__mux0021214_SPECSIG"/><failsig name="uc_intrface__mux0021210_SPECSIG"/><failsig name="uc_intrface__mux002129_SPECSIG"/><failsig name="uc_intrface__mux0021310_SPECSIG"/><failsig name="uc_intrface__mux0021312_SPECSIG"/><failsig name="uc_intrface__mux0021314_SPECSIG"/><failsig name="uc_intrface__mux002134_SPECSIG"/><failsig name="uc_intrface__mux0021315_SPECSIG"/><failsig name="uc_intrface__mux002133_SPECSIG"/><failsig name="uc_intrface__mux0021311_SPECSIG"/><failsig name="uc_intrface__mux002139_SPECSIG"/><failsig name="uc_intrface__mux002132_SPECSIG"/><failsig name="uc_intrface__mux0021313_SPECSIG"/><failsig name="uc_intrface__mux002131_SPECSIG"/><failsig name="uc_intrface__mux002144_SPECSIG"/><failsig name="uc_intrface__mux0021411_SPECSIG"/><failsig name="uc_intrface__mux002142_SPECSIG"/><failsig name="uc_intrface__mux002141_SPECSIG"/><failsig name="uc_intrface__mux002149_SPECSIG"/><failsig name="uc_intrface__mux0021415_SPECSIG"/><failsig name="uc_intrface__mux0021410_SPECSIG"/><failsig name="uc_intrface__mux0021412_SPECSIG"/><failsig name="uc_intrface__mux0021414_SPECSIG"/><failsig name="uc_intrface__mux002143_SPECSIG"/><failsig name="uc_intrface__mux0021413_SPECSIG"/><failsig name="uc_intrface__mux0021512_SPECSIG"/><failsig name="uc_intrface__mux0021514_SPECSIG"/><failsig name="uc_intrface__mux002151_SPECSIG"/><failsig name="uc_intrface__mux0021511_SPECSIG"/><failsig name="uc_intrface__mux0021510_SPECSIG"/><failsig name="uc_intrface__mux0021513_SPECSIG"/><failsig name="uc_intrface__mux002154_SPECSIG"/><failsig name="uc_intrface__mux002152_SPECSIG"/><failsig name="uc_intrface__mux0021515_SPECSIG"/><failsig name="uc_intrface__mux002159_SPECSIG"/><failsig name="uc_intrface__mux002153_SPECSIG"/><failsig name="uc_intrface__mux0021614_SPECSIG"/><failsig name="uc_intrface__mux0021610_SPECSIG"/><failsig name="uc_intrface__mux0021612_SPECSIG"/><failsig name="uc_intrface__mux0021613_SPECSIG"/><failsig name="uc_intrface__mux002169_SPECSIG"/><failsig name="uc_intrface__mux0021615_SPECSIG"/><failsig name="uc_intrface__mux002161_SPECSIG"/><failsig name="uc_intrface__mux0021611_SPECSIG"/><failsig name="uc_intrface__mux002162_SPECSIG"/><failsig name="uc_intrface__mux002164_SPECSIG"/><failsig name="uc_intrface__mux002163_SPECSIG"/><failsig name="uc_intrface__mux0021710_SPECSIG"/><failsig name="uc_intrface__mux0021712_SPECSIG"/><failsig name="uc_intrface__mux002174_SPECSIG"/><failsig name="uc_intrface__mux002173_SPECSIG"/><failsig name="uc_intrface__mux002179_SPECSIG"/><failsig name="uc_intrface__mux0021715_SPECSIG"/><failsig name="uc_intrface__mux0021713_SPECSIG"/><failsig name="uc_intrface__mux0021711_SPECSIG"/><failsig name="uc_intrface__mux002171_SPECSIG"/><failsig name="uc_intrface__mux0021714_SPECSIG"/><failsig name="uc_intrface__mux002172_SPECSIG"/><failsig name="uc_intrface__not0014"/><failsig name="uc_intrface__not0015"/><failsig name="uc_intrface__not0016"/><failsig name="uc_intrface__not0018"/><failsig name="uc_intrface__not0019"/><failsig name="uc_intrface__not00194"/><failsig name="uc_intrface__not0020"/><failsig name="uc_intrface__not00204"/><failsig name="uc_intrface__not0021"/><failsig name="uc_intrface__not00211"/><failsig name="uc_intrface__not00213"/><failsig name="uc_intrface__not00214"/><failsig name="uc_intrface__not00215"/><failsig name="uc_intrface__not00216"/><failsig name="uc_intrface__not0022"/><failsig name="uc_intrface__not00224"/><failsig name="uc_intrface__or0000"/><failsig name="uc_intrface__xor0012"/><failsig name="uc_intrface__xor00121"/><failsig name="uc_intrface__xor00127"/><failsig name="uc_intrface_address_low0_SPECSIG"/><failsig name="uc_intrface_address_low1_SPECSIG"/><failsig name="uc_intrface_address_low2_SPECSIG"/><failsig name="uc_intrface_address_low3_SPECSIG"/><failsig name="uc_intrface_address_low4_SPECSIG"/><failsig name="uc_intrface_address_low5_SPECSIG"/><failsig name="uc_intrface_address_low6_SPECSIG"/><failsig name="uc_intrface_address_low7_SPECSIG"/><failsig name="uc_intrface_address_match"/><failsig name="uc_intrface_bb"/><failsig name="uc_intrface_clkdiv0_SPECSIG"/><failsig name="uc_intrface_clkdiv1_SPECSIG"/><failsig name="uc_intrface_cntrl_en"/><failsig name="uc_intrface_cpha"/><failsig name="uc_intrface_cpol"/><failsig name="uc_intrface_data_in6_SPECSIG"/><failsig name="uc_intrface_data_oe"/><failsig name="uc_intrface_data_oe1"/><failsig name="uc_intrface_data_out0_SPECSIG"/><failsig name="uc_intrface_data_out1_SPECSIG"/><failsig name="uc_intrface_data_out2_SPECSIG"/><failsig name="uc_intrface_data_out3_SPECSIG"/><failsig name="uc_intrface_data_out4_SPECSIG"/><failsig name="uc_intrface_data_out5_SPECSIG"/><failsig name="uc_intrface_data_out6_SPECSIG"/><failsig name="uc_intrface_data_out7_SPECSIG"/><failsig name="uc_intrface_dt"/><failsig name="uc_intrface_int_n"/><failsig name="uc_intrface_inten"/><failsig name="uc_intrface_prs_state_FFd1"/><failsig name="uc_intrface_prs_state_FFd1-In_T"/><failsig name="uc_intrface_prs_state_FFd1-In_T1"/><failsig name="uc_intrface_prs_state_FFd1-In_T10"/><failsig name="uc_intrface_prs_state_FFd1-In_T5"/><failsig name="uc_intrface_prs_state_FFd1-In_T7"/><failsig name="uc_intrface_prs_state_FFd1-In_T8"/><failsig name="uc_intrface_prs_state_FFd1-In_T9"/><failsig name="uc_intrface_prs_state_FFd1QD_SPECSIG"/><failsig name="uc_intrface_prs_state_FFd2"/><failsig name="uc_intrface_prs_state_FFd2-In_T"/><failsig name="uc_intrface_prs_state_FFd2-In_T5"/><failsig name="uc_intrface_prs_state_FFd2-In_T6"/><failsig name="uc_intrface_prs_state_FFd2-In_T7"/><failsig name="uc_intrface_prs_state_FFd2-In_T8"/><failsig name="uc_intrface_prs_state_FFd2-In_T9"/><failsig name="uc_intrface_prs_state_FFd2QD_SPECSIG"/><failsig name="uc_intrface_rcv_cpol"/><failsig name="uc_intrface_rcv_en"/><failsig name="uc_intrface_rcv_full_reset"/><failsig name="uc_intrface_spien"/><failsig name="uc_intrface_spierr"/><failsig name="uc_intrface_spierr_N1"/><failsig name="uc_intrface_spierr_reset"/><failsig name="uc_intrface_spirr0_SPECSIG"/><failsig name="uc_intrface_spirr1_SPECSIG"/><failsig name="uc_intrface_spirr2_SPECSIG"/><failsig name="uc_intrface_spirr3_SPECSIG"/><failsig name="uc_intrface_spirr4_SPECSIG"/><failsig name="uc_intrface_spirr5_SPECSIG"/><failsig name="uc_intrface_spirr6_SPECSIG"/><failsig name="uc_intrface_spirr7_SPECSIG"/><failsig name="uc_intrface_spissr0_SPECSIG"/><failsig name="uc_intrface_spissr1_SPECSIG"/><failsig name="uc_intrface_spissr2_SPECSIG"/><failsig name="uc_intrface_spissr3_SPECSIG"/><failsig name="uc_intrface_spissr4_SPECSIG"/><failsig name="uc_intrface_spissr5_SPECSIG"/><failsig name="uc_intrface_spissr6_SPECSIG"/><failsig name="uc_intrface_spissr7_SPECSIG"/><failsig name="uc_intrface_spitr0_SPECSIG"/><failsig name="uc_intrface_spitr1_SPECSIG"/><failsig name="uc_intrface_spitr2_SPECSIG"/><failsig name="uc_intrface_spitr3_SPECSIG"/><failsig name="uc_intrface_spitr4_SPECSIG"/><failsig name="uc_intrface_spitr5_SPECSIG"/><failsig name="uc_intrface_spitr6_SPECSIG"/><failsig name="uc_intrface_spitr7_SPECSIG"/><failsig name="uc_intrface_ssel_en"/><failsig name="uc_intrface_start"/><failsig name="uc_intrface_stat_en"/><failsig name="uc_intrface_xmit_empty_reset"/><failsig name="uc_intrface_xmit_en"/></failuretable><unmapped_logic><pterm id="DummyFB_1_1"><signal id="psen_n"/><signal id="ale_n" negated="ON"/><signal id="addr5_SPECSIG" negated="ON"/><signal id="addr4_SPECSIG" negated="ON"/><signal id="addr3_SPECSIG" negated="ON"/><signal id="addr2_SPECSIG" negated="ON"/><signal id="addr1_SPECSIG" negated="ON"/><signal id="addr0_SPECSIG" negated="ON"/></pterm><unmapped_eqn sigUse="8"><equation id="uc_intrface__and000110"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="uc_intrface__mux002101_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="uc_intrface__mux0021012_SPECSIG"/></pterm><pterm id="DummyFB_1_3"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_4"><signal id="clk"/></pterm><pterm id="DummyFB_1_5"><signal id="uc_intrface__xor0012" negated="ON"/></pterm><pterm id="DummyFB_1_6"><signal id="uc_intrface_data_oe"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" sigUse="6"><equation id="addr_data0_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><reset><eq_pterm ptindx="DummyFB_1_3"/></reset><oe><eq_pterm ptindx="DummyFB_1_6"/></oe><ce><eq_pterm ptindx="DummyFB_1_5"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="uc_intrface__mux002111_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="uc_intrface__mux0021112_SPECSIG"/></pterm><pterm id="DummyFB_1_3"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_4"><signal id="clk"/></pterm><pterm id="DummyFB_1_5"><signal id="uc_intrface__xor0012" negated="ON"/></pterm><pterm id="DummyFB_1_6"><signal id="uc_intrface_data_oe"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" sigUse="6"><equation id="addr_data1_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><reset><eq_pterm ptindx="DummyFB_1_3"/></reset><oe><eq_pterm ptindx="DummyFB_1_6"/></oe><ce><eq_pterm ptindx="DummyFB_1_5"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="uc_intrface__mux002121_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="uc_intrface__mux0021215_SPECSIG"/></pterm><pterm id="DummyFB_1_3"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_4"><signal id="clk"/></pterm><pterm id="DummyFB_1_5"><signal id="uc_intrface__xor0012" negated="ON"/></pterm><pterm id="DummyFB_1_6"><signal id="uc_intrface_data_oe"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" sigUse="6"><equation id="addr_data2_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><reset><eq_pterm ptindx="DummyFB_1_3"/></reset><oe><eq_pterm ptindx="DummyFB_1_6"/></oe><ce><eq_pterm ptindx="DummyFB_1_5"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="uc_intrface__mux002131_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="uc_intrface__mux0021315_SPECSIG"/></pterm><pterm id="DummyFB_1_3"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_4"><signal id="clk"/></pterm><pterm id="DummyFB_1_5"><signal id="uc_intrface__xor0012" negated="ON"/></pterm><pterm id="DummyFB_1_6"><signal id="uc_intrface_data_oe"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" sigUse="6"><equation id="addr_data3_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><reset><eq_pterm ptindx="DummyFB_1_3"/></reset><oe><eq_pterm ptindx="DummyFB_1_6"/></oe><ce><eq_pterm ptindx="DummyFB_1_5"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="uc_intrface__mux002141_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="uc_intrface__mux0021415_SPECSIG"/></pterm><pterm id="DummyFB_1_3"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_4"><signal id="clk"/></pterm><pterm id="DummyFB_1_5"><signal id="uc_intrface__xor0012" negated="ON"/></pterm><pterm id="DummyFB_1_6"><signal id="uc_intrface_data_oe"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" sigUse="6"><equation id="addr_data4_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><reset><eq_pterm ptindx="DummyFB_1_3"/></reset><oe><eq_pterm ptindx="DummyFB_1_6"/></oe><ce><eq_pterm ptindx="DummyFB_1_5"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="uc_intrface__mux002151_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="uc_intrface__mux0021515_SPECSIG"/></pterm><pterm id="DummyFB_1_3"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_4"><signal id="clk"/></pterm><pterm id="DummyFB_1_5"><signal id="uc_intrface__xor0012" negated="ON"/></pterm><pterm id="DummyFB_1_6"><signal id="uc_intrface_data_oe"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" sigUse="6"><equation id="addr_data5_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><reset><eq_pterm ptindx="DummyFB_1_3"/></reset><oe><eq_pterm ptindx="DummyFB_1_6"/></oe><ce><eq_pterm ptindx="DummyFB_1_5"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="uc_intrface__mux002161_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="uc_intrface__mux0021615_SPECSIG"/></pterm><pterm id="DummyFB_1_3"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_4"><signal id="clk"/></pterm><pterm id="DummyFB_1_5"><signal id="uc_intrface__xor0012" negated="ON"/></pterm><pterm id="DummyFB_1_6"><signal id="uc_intrface_data_oe"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" sigUse="6"><equation id="addr_data6_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><reset><eq_pterm ptindx="DummyFB_1_3"/></reset><oe><eq_pterm ptindx="DummyFB_1_6"/></oe><ce><eq_pterm ptindx="DummyFB_1_5"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="uc_intrface__mux002171_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="uc_intrface__mux0021715_SPECSIG"/></pterm><pterm id="DummyFB_1_3"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_4"><signal id="clk"/></pterm><pterm id="DummyFB_1_5"><signal id="uc_intrface__xor0012" negated="ON"/></pterm><pterm id="DummyFB_1_6"><signal id="uc_intrface_data_oe"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" sigUse="6"><equation id="addr_data7_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><reset><eq_pterm ptindx="DummyFB_1_3"/></reset><oe><eq_pterm ptindx="DummyFB_1_6"/></oe><ce><eq_pterm ptindx="DummyFB_1_5"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="spi_intrface_spi_ctrl_sm_spi_state_FFd3" negated="ON"/><signal id="spi_intrface_spi_ctrl_sm_spi_state_FFd4" negated="ON"/><signal id="spi_intrface_spi_ctrl_sm_bit_cnt0_SPECSIG" negated="ON"/><signal id="spi_intrface_spi_ctrl_sm_bit_cnt1_SPECSIG" negated="ON"/><signal id="spi_intrface_spi_ctrl_sm_bit_cnt2_SPECSIG" negated="ON"/><signal id="spi_intrface_spi_ctrl_sm_bit_cnt3_SPECSIG"/></pterm><unmapped_eqn sigUse="6"><equation id="spi_intrface_spi_ctrl_sm_spi_state_FFd4-In_T31"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="spi_intrface_SCK_GEN_Mmux__mux0005_Result13"/></pterm><pterm id="DummyFB_1_2"><signal id="spi_intrface_SCK_GEN_Mmux__mux0005_Result15"/></pterm><pterm id="DummyFB_1_3"><signal id="uc_intrface_spien" negated="ON"/></pterm><pterm id="DummyFB_1_4"><signal id="clk"/></pterm><pterm id="DummyFB_1_5"><signal id="spi_intrface_spi_ctrl_sm_ss_in_int"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" sigUse="5"><equation id="sck" regUse="DFF"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><reset><eq_pterm ptindx="DummyFB_1_3"/></reset><oe><eq_pterm ptindx="DummyFB_1_5"/></oe></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="uc_intrface_spissr0_SPECSIG" negated="ON"/></pterm><pterm id="DummyFB_1_2"><signal id="ss_n_int"/></pterm><pterm id="DummyFB_1_3"><signal id="uc_intrface_spien" negated="ON"/></pterm><pterm id="DummyFB_1_4"><signal id="clk" negated="ON"/></pterm><pterm id="DummyFB_1_5"><signal id="spi_intrface_spi_ctrl_sm_ss_in_int"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" sigUse="5"><equation id="ss_n0_SPECSIG" regUse="DFFS_SPECSIG"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><set><eq_pterm ptindx="DummyFB_1_3"/></set><oe><eq_pterm ptindx="DummyFB_1_5"/></oe></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="uc_intrface_spissr1_SPECSIG" negated="ON"/></pterm><pterm id="DummyFB_1_2"><signal id="ss_n_int"/></pterm><pterm id="DummyFB_1_3"><signal id="uc_intrface_spien" negated="ON"/></pterm><pterm id="DummyFB_1_4"><signal id="clk" negated="ON"/></pterm><pterm id="DummyFB_1_5"><signal id="spi_intrface_spi_ctrl_sm_ss_in_int"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" sigUse="5"><equation id="ss_n1_SPECSIG" regUse="DFFS_SPECSIG"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><set><eq_pterm ptindx="DummyFB_1_3"/></set><oe><eq_pterm ptindx="DummyFB_1_5"/></oe></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="uc_intrface_spissr2_SPECSIG" negated="ON"/></pterm><pterm id="DummyFB_1_2"><signal id="ss_n_int"/></pterm><pterm id="DummyFB_1_3"><signal id="uc_intrface_spien" negated="ON"/></pterm><pterm id="DummyFB_1_4"><signal id="clk" negated="ON"/></pterm><pterm id="DummyFB_1_5"><signal id="spi_intrface_spi_ctrl_sm_ss_in_int"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" sigUse="5"><equation id="ss_n2_SPECSIG" regUse="DFFS_SPECSIG"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><set><eq_pterm ptindx="DummyFB_1_3"/></set><oe><eq_pterm ptindx="DummyFB_1_5"/></oe></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="uc_intrface_spissr3_SPECSIG" negated="ON"/></pterm><pterm id="DummyFB_1_2"><signal id="ss_n_int"/></pterm><pterm id="DummyFB_1_3"><signal id="uc_intrface_spien" negated="ON"/></pterm><pterm id="DummyFB_1_4"><signal id="clk" negated="ON"/></pterm><pterm id="DummyFB_1_5"><signal id="spi_intrface_spi_ctrl_sm_ss_in_int"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" sigUse="5"><equation id="ss_n3_SPECSIG" regUse="DFFS_SPECSIG"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><set><eq_pterm ptindx="DummyFB_1_3"/></set><oe><eq_pterm ptindx="DummyFB_1_5"/></oe></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="uc_intrface_spissr4_SPECSIG" negated="ON"/></pterm><pterm id="DummyFB_1_2"><signal id="ss_n_int"/></pterm><pterm id="DummyFB_1_3"><signal id="uc_intrface_spien" negated="ON"/></pterm><pterm id="DummyFB_1_4"><signal id="clk" negated="ON"/></pterm><pterm id="DummyFB_1_5"><signal id="spi_intrface_spi_ctrl_sm_ss_in_int"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" sigUse="5"><equation id="ss_n4_SPECSIG" regUse="DFFS_SPECSIG"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><set><eq_pterm ptindx="DummyFB_1_3"/></set><oe><eq_pterm ptindx="DummyFB_1_5"/></oe></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="uc_intrface_spissr5_SPECSIG" negated="ON"/></pterm><pterm id="DummyFB_1_2"><signal id="ss_n_int"/></pterm><pterm id="DummyFB_1_3"><signal id="uc_intrface_spien" negated="ON"/></pterm><pterm id="DummyFB_1_4"><signal id="clk" negated="ON"/></pterm><pterm id="DummyFB_1_5"><signal id="spi_intrface_spi_ctrl_sm_ss_in_int"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" sigUse="5"><equation id="ss_n5_SPECSIG" regUse="DFFS_SPECSIG"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><set><eq_pterm ptindx="DummyFB_1_3"/></set><oe><eq_pterm ptindx="DummyFB_1_5"/></oe></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="uc_intrface_spissr6_SPECSIG" negated="ON"/></pterm><pterm id="DummyFB_1_2"><signal id="ss_n_int"/></pterm><pterm id="DummyFB_1_3"><signal id="uc_intrface_spien" negated="ON"/></pterm><pterm id="DummyFB_1_4"><signal id="clk" negated="ON"/></pterm><pterm id="DummyFB_1_5"><signal id="spi_intrface_spi_ctrl_sm_ss_in_int"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" sigUse="5"><equation id="ss_n6_SPECSIG" regUse="DFFS_SPECSIG"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><set><eq_pterm ptindx="DummyFB_1_3"/></set><oe><eq_pterm ptindx="DummyFB_1_5"/></oe></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="uc_intrface_spissr7_SPECSIG" negated="ON"/></pterm><pterm id="DummyFB_1_2"><signal id="ss_n_int"/></pterm><pterm id="DummyFB_1_3"><signal id="uc_intrface_spien" negated="ON"/></pterm><pterm id="DummyFB_1_4"><signal id="clk" negated="ON"/></pterm><pterm id="DummyFB_1_5"><signal id="spi_intrface_spi_ctrl_sm_ss_in_int"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" sigUse="5"><equation id="ss_n7_SPECSIG" regUse="DFFS_SPECSIG"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><set><eq_pterm ptindx="DummyFB_1_3"/></set><oe><eq_pterm ptindx="DummyFB_1_5"/></oe></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="uc_intrface_cntrl_en" negated="ON"/><signal id="uc_intrface_rcv_en" negated="ON"/><signal id="uc_intrface_ssel_en" negated="ON"/><signal id="uc_intrface_stat_en" negated="ON"/><signal id="uc_intrface_xmit_en" negated="ON"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface__xor00127"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="uc_intrface_rcv_full_reset"/></pterm><pterm id="DummyFB_1_2"><signal id="uc_intrface_spien" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="spi_intrface_spi_ctrl_sm__not0003"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" sigUse="4"><equation id="rcv_full" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="uc_intrface_rcv_full_reset" negated="ON"/></pterm><pterm id="DummyFB_1_2"><signal id="uc_intrface_spierr_reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="uc_intrface_xmit_empty_reset" negated="ON"/></pterm><pterm id="DummyFB_1_4"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_5"><signal id="clk"/></pterm><pterm id="DummyFB_1_6"><signal id="uc_intrface__not0021"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" sigUse="6"><equation id="int_n" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/><eq_pterm ptindx="DummyFB_1_3"/></d2><clk><eq_pterm ptindx="DummyFB_1_5"/></clk><set><eq_pterm ptindx="DummyFB_1_4"/></set><ce><eq_pterm ptindx="DummyFB_1_6"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="spi_intrface_xmit_shift_reg_data_int7_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="uc_intrface_spien" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="spi_intrface_spi_ctrl_sm_ss_in_int"/></pterm><unmapped_eqn iostd="LVCMOS18" output="ON" sigUse="4"><equation id="mosi" regUse="DFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><oe><eq_pterm ptindx="DummyFB_1_4"/></oe></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="wr_n" negated="ON"/><signal id="addr_data7PIN_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface__not0014"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_spien" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="spi_intrface_spi_ctrl_sm_spi_state_FFd4QD_SPECSIG"/><signal id="spi_intrface_spi_ctrl_sm_spi_state_FFd4" negated="ON"/></pterm><pterm id="DummyFB_1_2"><signal id="spi_intrface_spi_ctrl_sm_spi_state_FFd4QD_SPECSIG" negated="ON"/><signal id="spi_intrface_spi_ctrl_sm_spi_state_FFd4"/></pterm><pterm id="DummyFB_1_3"><signal id="spi_intrface_xmit_shift_reg__xor0001"/></pterm><pterm id="DummyFB_1_4"><signal id="clk"/></pterm><unmapped_eqn sigUse="4"><equation id="spi_intrface_spi_ctrl_sm_spi_state_FFd4" regUse="TFF"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><reset><eq_pterm ptindx="DummyFB_1_3"/></reset></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="spi_intrface_spi_ctrl_sm_spi_state_FFd2QD_SPECSIG"/><signal id="spi_intrface_spi_ctrl_sm_spi_state_FFd2" negated="ON"/></pterm><pterm id="DummyFB_1_2"><signal id="spi_intrface_spi_ctrl_sm_spi_state_FFd2QD_SPECSIG" negated="ON"/><signal id="spi_intrface_spi_ctrl_sm_spi_state_FFd2"/></pterm><pterm id="DummyFB_1_3"><signal id="spi_intrface_xmit_shift_reg__xor0001"/></pterm><pterm id="DummyFB_1_4"><signal id="clk"/></pterm><unmapped_eqn sigUse="4"><equation id="spi_intrface_spi_ctrl_sm_spi_state_FFd2" regUse="TFF"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><reset><eq_pterm ptindx="DummyFB_1_3"/></reset></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="spi_intrface_spi_ctrl_sm_spi_state_FFd3QD_SPECSIG"/><signal id="spi_intrface_spi_ctrl_sm_spi_state_FFd3" negated="ON"/></pterm><pterm id="DummyFB_1_2"><signal id="spi_intrface_spi_ctrl_sm_spi_state_FFd3QD_SPECSIG" negated="ON"/><signal id="spi_intrface_spi_ctrl_sm_spi_state_FFd3"/></pterm><pterm id="DummyFB_1_3"><signal id="spi_intrface_xmit_shift_reg__xor0001"/></pterm><pterm id="DummyFB_1_4"><signal id="clk"/></pterm><unmapped_eqn sigUse="4"><equation id="spi_intrface_spi_ctrl_sm_spi_state_FFd3" regUse="TFF"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><reset><eq_pterm ptindx="DummyFB_1_3"/></reset></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="spi_intrface_spi_ctrl_sm_spi_state_FFd1QD_SPECSIG"/><signal id="spi_intrface_spi_ctrl_sm_spi_state_FFd1" negated="ON"/></pterm><pterm id="DummyFB_1_2"><signal id="spi_intrface_spi_ctrl_sm_spi_state_FFd1QD_SPECSIG" negated="ON"/><signal id="spi_intrface_spi_ctrl_sm_spi_state_FFd1"/></pterm><pterm id="DummyFB_1_3"><signal id="spi_intrface_xmit_shift_reg__xor0001"/></pterm><pterm id="DummyFB_1_4"><signal id="clk"/></pterm><unmapped_eqn sigUse="4"><equation id="spi_intrface_spi_ctrl_sm_spi_state_FFd1" regUse="TFF"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><reset><eq_pterm ptindx="DummyFB_1_3"/></reset></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="uc_intrface_prs_state_FFd2"/><signal id="uc_intrface_prs_state_FFd2QD_SPECSIG" negated="ON"/></pterm><pterm id="DummyFB_1_2"><signal id="uc_intrface_prs_state_FFd2" negated="ON"/><signal id="uc_intrface_prs_state_FFd2QD_SPECSIG"/></pterm><pterm id="DummyFB_1_3"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_4"><signal id="clk"/></pterm><unmapped_eqn sigUse="4"><equation id="uc_intrface_prs_state_FFd2" regUse="TFF"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><reset><eq_pterm ptindx="DummyFB_1_3"/></reset></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="uc_intrface_prs_state_FFd1"/><signal id="uc_intrface_prs_state_FFd1QD_SPECSIG" negated="ON"/></pterm><pterm id="DummyFB_1_2"><signal id="uc_intrface_prs_state_FFd1" negated="ON"/><signal id="uc_intrface_prs_state_FFd1QD_SPECSIG"/></pterm><pterm id="DummyFB_1_3"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_4"><signal id="clk"/></pterm><unmapped_eqn sigUse="4"><equation id="uc_intrface_prs_state_FFd1" regUse="TFF"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><reset><eq_pterm ptindx="DummyFB_1_3"/></reset></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="wr_n" negated="ON"/><signal id="addr_data2PIN_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface__not0014"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_cpha" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="wr_n" negated="ON"/><signal id="addr_data4PIN_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface__not0014"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_clkdiv1_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="wr_n" negated="ON"/><signal id="addr_data1PIN_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface__not0014"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_cpol" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="wr_n" negated="ON"/><signal id="addr_data5PIN_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface__not0014"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_start" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="wr_n" negated="ON"/><signal id="addr_data0PIN_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface__not0014"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_rcv_cpol" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="wr_n" negated="ON"/><signal id="addr_data3PIN_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface__not0014"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_clkdiv0_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="spi_intrface_spi_ctrl_sm_bit_cnt0_SPECSIG" negated="ON"/></pterm><pterm id="DummyFB_1_2"><signal id="spi_intrface_spi_ctrl_sm_bit_cnt_reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="spi_intrface_sck_1"/></pterm><pterm id="DummyFB_1_4"><signal id="spi_intrface_spi_ctrl_sm_bit_cnt_rst"/></pterm><unmapped_eqn sigUse="4"><equation id="spi_intrface_spi_ctrl_sm_bit_cnt0_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="spi_intrface_spi_ctrl_sm_bit_cnt0_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="spi_intrface_spi_ctrl_sm_bit_cnt1_SPECSIG"/></pterm><pterm id="DummyFB_1_3"><signal id="spi_intrface_spi_ctrl_sm_bit_cnt_reset" negated="ON"/></pterm><pterm id="DummyFB_1_4"><signal id="spi_intrface_sck_1"/></pterm><pterm id="DummyFB_1_5"><signal id="spi_intrface_spi_ctrl_sm_bit_cnt_rst"/></pterm><unmapped_eqn sigUse="5"><equation id="spi_intrface_spi_ctrl_sm_bit_cnt1_SPECSIG" regUse="DEFF"><d1><eq_pterm ptindx="DummyFB_1_1"/></d1><d2><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><reset><eq_pterm ptindx="DummyFB_1_3"/></reset><ce><eq_pterm ptindx="DummyFB_1_5"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="spi_intrface_spi_ctrl_sm_BIT_CNTRq_int_Madd__add0000__and0000_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="spi_intrface_spi_ctrl_sm_bit_cnt2_SPECSIG"/></pterm><pterm id="DummyFB_1_3"><signal id="spi_intrface_spi_ctrl_sm_bit_cnt_reset" negated="ON"/></pterm><pterm id="DummyFB_1_4"><signal id="spi_intrface_sck_1"/></pterm><pterm id="DummyFB_1_5"><signal id="spi_intrface_spi_ctrl_sm_bit_cnt_rst"/></pterm><unmapped_eqn sigUse="5"><equation id="spi_intrface_spi_ctrl_sm_bit_cnt2_SPECSIG" regUse="DEFF"><d1><eq_pterm ptindx="DummyFB_1_1"/></d1><d2><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><reset><eq_pterm ptindx="DummyFB_1_3"/></reset><ce><eq_pterm ptindx="DummyFB_1_5"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="uc_intrface_prs_state_FFd1" negated="ON"/></pterm><pterm id="DummyFB_1_2"><signal id="uc_intrface_prs_state_FFd2" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_4"><signal id="clk"/></pterm><pterm id="DummyFB_1_5"><signal id="uc_intrface__not0019"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_rcv_full_reset" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><reset><eq_pterm ptindx="DummyFB_1_3"/></reset><ce><eq_pterm ptindx="DummyFB_1_5"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="uc_intrface_data_in6_SPECSIG" negated="ON"/><signal id="uc_intrface_Mrom__mux0025__cmp_eq00001"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface__not0022"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_spierr_reset" regUse="DEFF" negated="ON"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="spi_intrface_rcv_shift_regshift_in1_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="spi_intrface_rcv_shift_regshift_in3_SPECSIG"/></pterm><pterm id="DummyFB_1_3"><signal id="spi_intrface_rcv_shift_reg_xor0000_SPECSIG"/></pterm><pterm id="DummyFB_1_4"><signal id="sckPIN_SPECSIG"/></pterm><pterm id="DummyFB_1_5"><signal id="ss_n_int" negated="ON"/></pterm><unmapped_eqn sigUse="5"><equation id="rcv_data1_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><reset><eq_pterm ptindx="DummyFB_1_3"/></reset><ce><eq_pterm ptindx="DummyFB_1_5"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="rcv_data1_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="spi_intrface_rcv_shift_reg_xor0000_SPECSIG"/></pterm><pterm id="DummyFB_1_3"><signal id="sckPIN_SPECSIG"/></pterm><pterm id="DummyFB_1_4"><signal id="ss_n_int" negated="ON"/></pterm><unmapped_eqn sigUse="4"><equation id="rcv_data2_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="rcv_data2_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="spi_intrface_rcv_shift_reg_xor0000_SPECSIG"/></pterm><pterm id="DummyFB_1_3"><signal id="sckPIN_SPECSIG"/></pterm><pterm id="DummyFB_1_4"><signal id="ss_n_int" negated="ON"/></pterm><unmapped_eqn sigUse="4"><equation id="rcv_data3_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="rcv_data3_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="spi_intrface_rcv_shift_reg_xor0000_SPECSIG"/></pterm><pterm id="DummyFB_1_3"><signal id="sckPIN_SPECSIG"/></pterm><pterm id="DummyFB_1_4"><signal id="ss_n_int" negated="ON"/></pterm><unmapped_eqn sigUse="4"><equation id="rcv_data4_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="rcv_data4_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="spi_intrface_rcv_shift_reg_xor0000_SPECSIG"/></pterm><pterm id="DummyFB_1_3"><signal id="sckPIN_SPECSIG"/></pterm><pterm id="DummyFB_1_4"><signal id="ss_n_int" negated="ON"/></pterm><unmapped_eqn sigUse="4"><equation id="rcv_data5_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="rcv_data5_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="spi_intrface_rcv_shift_reg_xor0000_SPECSIG"/></pterm><pterm id="DummyFB_1_3"><signal id="sckPIN_SPECSIG"/></pterm><pterm id="DummyFB_1_4"><signal id="ss_n_int" negated="ON"/></pterm><unmapped_eqn sigUse="4"><equation id="rcv_data6_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="spi_intrface_spi_ctrl_sm_BIT_CNTRq_int_Madd__add0000__and0001_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="spi_intrface_spi_ctrl_sm_bit_cnt3_SPECSIG"/></pterm><pterm id="DummyFB_1_3"><signal id="spi_intrface_spi_ctrl_sm_bit_cnt_reset" negated="ON"/></pterm><pterm id="DummyFB_1_4"><signal id="spi_intrface_sck_1"/></pterm><pterm id="DummyFB_1_5"><signal id="spi_intrface_spi_ctrl_sm_bit_cnt_rst"/></pterm><unmapped_eqn sigUse="5"><equation id="spi_intrface_spi_ctrl_sm_bit_cnt3_SPECSIG" regUse="DEFF"><d1><eq_pterm ptindx="DummyFB_1_1"/></d1><d2><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><reset><eq_pterm ptindx="DummyFB_1_3"/></reset><ce><eq_pterm ptindx="DummyFB_1_5"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="wr_n" negated="ON"/><signal id="addr_data6PIN_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface__not0014"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_inten" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="uc_intrface_spierr_reset"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface_spierr_N1"/></pterm><unmapped_eqn sigUse="4"><equation id="uc_intrface_spierr" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="wr_n" negated="ON"/><signal id="addr_data0PIN_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface__not0018"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_spissr0_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="wr_n" negated="ON"/><signal id="addr_data1PIN_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface__not0018"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_spissr1_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="wr_n" negated="ON"/><signal id="addr_data2PIN_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface__not0018"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_spissr2_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="wr_n" negated="ON"/><signal id="addr_data3PIN_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface__not0018"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_spissr3_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="wr_n" negated="ON"/><signal id="addr_data4PIN_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface__not0018"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_spissr4_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="wr_n" negated="ON"/><signal id="addr_data5PIN_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface__not0018"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_spissr5_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="wr_n" negated="ON"/><signal id="addr_data6PIN_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface__not0018"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_spissr6_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="wr_n" negated="ON"/><signal id="addr_data7PIN_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface__not0018"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_spissr7_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="wr_n" negated="ON"/><signal id="addr_data0PIN_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface__not0016"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_spitr0_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="wr_n" negated="ON"/><signal id="addr_data1PIN_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface__not0016"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_spitr1_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="wr_n" negated="ON"/><signal id="addr_data2PIN_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface__not0016"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_spitr2_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="wr_n" negated="ON"/><signal id="addr_data3PIN_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface__not0016"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_spitr3_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="wr_n" negated="ON"/><signal id="addr_data4PIN_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface__not0016"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_spitr4_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="wr_n" negated="ON"/><signal id="addr_data5PIN_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface__not0016"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_spitr5_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="wr_n" negated="ON"/><signal id="addr_data6PIN_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface__not0016"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_spitr6_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="wr_n" negated="ON"/><signal id="addr_data7PIN_SPECSIG"/></pterm><pterm id="DummyFB_1_2"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="clk"/></pterm><pterm id="DummyFB_1_4"><signal id="uc_intrface__not0016"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_spitr7_SPECSIG" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/></d2><clk><eq_pterm ptindx="DummyFB_1_3"/></clk><reset><eq_pterm ptindx="DummyFB_1_2"/></reset><ce><eq_pterm ptindx="DummyFB_1_4"/></ce></equation></unmapped_eqn><pterm id="DummyFB_1_1"><signal id="uc_intrface_prs_state_FFd1" negated="ON"/></pterm><pterm id="DummyFB_1_2"><signal id="uc_intrface_prs_state_FFd2" negated="ON"/></pterm><pterm id="DummyFB_1_3"><signal id="reset" negated="ON"/></pterm><pterm id="DummyFB_1_4"><signal id="clk"/></pterm><pterm id="DummyFB_1_5"><signal id="uc_intrface__not0020"/></pterm><unmapped_eqn sigUse="5"><equation id="uc_intrface_xmit_empty_reset" regUse="DEFF"><d2><eq_pterm ptindx="DummyFB_1_1"/><eq_pterm ptindx="DummyFB_1_2"/></d2><clk><eq_pterm ptindx="DummyFB_1_4"/></clk><reset><eq_pter