spi_master.blx

spi总线的vhdl代码

00 1
.names "clk"  "spi_intrface_spi_ctrl_sm_ss_in_int".CLK
1 1
.names "uc_intrface_spien".Q  "spi_intrface_spi_ctrl_sm_ss_in_int".AP
0 1
.names "uc_intrface_clkdiv<1>".Q "uc_intrface_clkdiv<0>".Q 
       "spi_intrface_SCK_GEN_clk_cnt<1>".Q "spi_intrface_SCK_GEN_clk_cnt<2>".Q 
       "spi_intrface_SCK_GEN_clk_cnt<3>".Q "spi_intrface_SCK_GEN_clk_cnt<4>".Q 
        "spi_intrface_SCK_GEN_sck_int".D-
000--- 1
01-0-- 1
10--0- 1
11---0 1
.names "clk"  "spi_intrface_SCK_GEN_sck_int".CLK
1 1
.names "uc_intrface_spien".Q  "spi_intrface_SCK_GEN_sck_int".AR
0 1
.names "sck".Q  "spi_intrface_SCK_GEN_sck_d1".D
1 1
.names "clk"  "spi_intrface_SCK_GEN_sck_d1".CLK
1 1
.names "uc_intrface_spien".Q  "spi_intrface_SCK_GEN_sck_d1".AR
0 1
.names "spi_intrface_SCK_GEN_sck_int".Q  "spi_intrface_SCK_GEN_sck_int_d1".D
1 1
.names "clk"  "spi_intrface_SCK_GEN_sck_int_d1".CLK
1 1
.names "uc_intrface_spien".Q  "spi_intrface_SCK_GEN_sck_int_d1".AR
0 1
.names "sck".PIN  "spi_intrface_rcv_shift_reg/rcv_bitcnt_int<0>".CLK
1 1
.names "spi_intrface_rcv_shift_reg/_or0000" 
        "spi_intrface_rcv_shift_reg/rcv_bitcnt_int<0>".AR
0 1
.names "addr_data<0>".PIN  "uc_intrface_address_low<0>".D
1 1
.names "ale_n"  "uc_intrface_address_low<0>".CLK-
1 1
.names "reset"  "uc_intrface_address_low<0>".AR
0 1
.names "addr_data<1>".PIN  "uc_intrface_address_low<1>".D
1 1
.names "ale_n"  "uc_intrface_address_low<1>".CLK-
1 1
.names "reset"  "uc_intrface_address_low<1>".AR
0 1
.names "addr_data<2>".PIN  "uc_intrface_address_low<2>".D
1 1
.names "ale_n"  "uc_intrface_address_low<2>".CLK-
1 1
.names "reset"  "uc_intrface_address_low<2>".AR
0 1
.names "addr_data<3>".PIN  "uc_intrface_address_low<3>".D
1 1
.names "ale_n"  "uc_intrface_address_low<3>".CLK-
1 1
.names "reset"  "uc_intrface_address_low<3>".AR
0 1
.names "addr_data<4>".PIN  "uc_intrface_address_low<4>".D
1 1
.names "ale_n"  "uc_intrface_address_low<4>".CLK-
1 1
.names "reset"  "uc_intrface_address_low<4>".AR
0 1
.names "addr_data<5>".PIN  "uc_intrface_address_low<5>".D
1 1
.names "ale_n"  "uc_intrface_address_low<5>".CLK-
1 1
.names "reset"  "uc_intrface_address_low<5>".AR
0 1
.names "addr_data<6>".PIN  "uc_intrface_address_low<6>".D
1 1
.names "ale_n"  "uc_intrface_address_low<6>".CLK-
1 1
.names "reset"  "uc_intrface_address_low<6>".AR
0 1
.names "addr_data<7>".PIN  "uc_intrface_address_low<7>".D
1 1
.names "ale_n"  "uc_intrface_address_low<7>".CLK-
1 1
.names "reset"  "uc_intrface_address_low<7>".AR
0 1
.names "clk"  "spi_intrface_SCK_GEN_clk_cnt<1>".CLK
1 1
.names "N_PZ_1007"  "spi_intrface_SCK_GEN_clk_cnt<1>".AR
0 1
.names "clk"  "spi_intrface_SCK_GEN_clk_cnt<2>".CLK
1 1
.names "N_PZ_1007"  "spi_intrface_SCK_GEN_clk_cnt<2>".AR
0 1
.names "clk"  "spi_intrface_SCK_GEN_clk_cnt<3>".CLK
1 1
.names "N_PZ_1007"  "spi_intrface_SCK_GEN_clk_cnt<3>".AR
0 1
.names "sck".PIN  "spi_intrface_rcv_shift_reg/rcv_bitcnt_int<1>".CLK
1 1
.names "spi_intrface_rcv_shift_reg/_or0000" 
        "spi_intrface_rcv_shift_reg/rcv_bitcnt_int<1>".AR
0 1
.names "clk"  "spi_intrface_SCK_GEN_CLK_DIVDR/qout<0>".CLK
1 1
.names "N_PZ_1007"  "spi_intrface_SCK_GEN_CLK_DIVDR/qout<0>".AR
0 1
.names "clk"  "spi_intrface_SCK_GEN_clk_cnt<4>".CLK
1 1
.names "N_PZ_1007"  "spi_intrface_SCK_GEN_clk_cnt<4>".AR
0 1
.names "sck".PIN  "spi_intrface_rcv_shift_reg/rcv_bitcnt_int<2>".CLK
1 1
.names "spi_intrface_rcv_shift_reg/_or0000" 
        "spi_intrface_rcv_shift_reg/rcv_bitcnt_int<2>".AR
0 1
.names "sck".Q "spi_intrface_spi_ctrl_sm_spi_state_FFd4".Q 
       "spi_intrface_spi_ctrl_sm_spi_state_FFd2".Q 
       "spi_intrface_spi_ctrl_sm_spi_state_FFd3".Q "uc_intrface_cpha".Q 
       "uc_intrface_clkdiv<1>".Q "uc_intrface_cpol".Q "uc_intrface_clkdiv<0>".Q 
       "spi_intrface_SCK_GEN_sck_d1".Q "spi_intrface_SCK_GEN_clk_cnt<1>".Q 
       "spi_intrface_SCK_GEN_clk_cnt<2>".Q "spi_intrface_SCK_GEN_clk_cnt<3>".Q 
       "spi_intrface_SCK_GEN_clk_cnt<4>".Q "N_PZ_665"  "spi_intrface_SCK_GEN_sck_0".D-
--0----------- 1
-1-1---------- 1
-----0-0-1---- 1
-----0-1--1--- 1
-----1-0---1-- 1
-----1-1----1- 1
---11--------0 1
0--1--0-1----0 1
1--1--1-0----0 1
.names "clk"  "spi_intrface_SCK_GEN_sck_0".CLK
1 1
.names "uc_intrface_spien".Q  "spi_intrface_SCK_GEN_sck_0".AR
0 1
.names "psen_n" "ale_n" "addr<5>" "addr<4>" "addr<3>" "addr<2>" "addr<1>" "addr<0>" 
       "addr<7>" "addr<6>"  "uc_intrface_address_match".D
1000000000 1
.names "clk"  "uc_intrface_address_match".CLK
1 1
.names "reset"  "uc_intrface_address_match".AR
0 1
.names "psen_n" "ale_n" "addr<5>" "addr<4>" "addr<3>" "addr<2>" "addr<1>" "addr<0>" 
       "addr<7>" "addr<6>" "uc_intrface_address_low<0>".Q 
       "uc_intrface_address_low<1>".Q "uc_intrface_address_low<2>".Q 
       "uc_intrface_address_low<3>".Q "uc_intrface_address_low<4>".Q 
       "uc_intrface_address_low<5>".Q "uc_intrface_address_low<6>".Q 
       "uc_intrface_address_low<7>".Q  "uc_intrface_cntrl_en".D
100000000000100001 1
.names "clk"  "uc_intrface_cntrl_en".CLK
1 1
.names "reset"  "uc_intrface_cntrl_en".AR
0 1
.names "miso"  "spi_intrface_rcv_shift_reg/miso_neg".D
1 1
.names "sck".PIN  "spi_intrface_rcv_shift_reg/miso_neg".CLK-
1 1
.names "N_PZ_1007"  "spi_intrface_rcv_shift_reg/miso_neg".AR
0 1
.names "miso"  "spi_intrface_rcv_shift_reg/miso_pos".D
1 1
.names "sck".PIN  "spi_intrface_rcv_shift_reg/miso_pos".CLK
1 1
.names "N_PZ_1007"  "spi_intrface_rcv_shift_reg/miso_pos".AR
0 1
.names "ss_in_n"  "spi_intrface_spi_ctrl_sm_ss_in_neg".D
1 1
.names "clk"  "spi_intrface_spi_ctrl_sm_ss_in_neg".CLK-
1 1
.names "uc_intrface_spien".Q  "spi_intrface_spi_ctrl_sm_ss_in_neg".AP
0 1
.names "ss_in_n"  "spi_intrface_spi_ctrl_sm_ss_in_pos".D
1 1
.names "clk"  "spi_intrface_spi_ctrl_sm_ss_in_pos".CLK
1 1
.names "uc_intrface_spien".Q  "spi_intrface_spi_ctrl_sm_ss_in_pos".AP
0 1
.names "N_PZ_656"  "uc_intrface_bb".D
0 1
.names "clk"  "uc_intrface_bb".CLK
1 1
.names "reset"  "uc_intrface_bb".AR
0 1
.names "spi_intrface_spi_ctrl_sm_spi_state_FFd4".Q 
       "spi_intrface_spi_ctrl_sm_spi_state_FFd2".Q 
       "spi_intrface_spi_ctrl_sm_spi_state_FFd3".Q  "uc_intrface_dt".D
11- 1
-11 1
.names "clk"  "uc_intrface_dt".CLK
1 1
.names "reset"  "uc_intrface_dt".AR
0 1
.names  "spi_intrface_rcv_shift_reg/rcv_bitcnt_int<0>".T
1
.names  "spi_intrface_SCK_GEN_CLK_DIVDR/qout<0>".T
1
.names "spi_intrface_SCK_GEN_CLK_DIVDR/qout<0>".Q  "spi_intrface_SCK_GEN_clk_cnt<1>".T
1 1
.names "spi_intrface_SCK_GEN_CLK_DIVDR/qout<0>".Q "spi_intrface_SCK_GEN_clk_cnt<1>".Q 
        "spi_intrface_SCK_GEN_clk_cnt<2>".T
11 1
.names "spi_intrface_SCK_GEN_CLK_DIVDR/qout<0>".Q "spi_intrface_SCK_GEN_clk_cnt<1>".Q 
       "spi_intrface_SCK_GEN_clk_cnt<2>".Q  "spi_intrface_SCK_GEN_clk_cnt<3>".T
111 1
.names "spi_intrface_rcv_shift_reg/rcv_bitcnt_int<0>".Q 
        "spi_intrface_rcv_shift_reg/rcv_bitcnt_int<1>".T
1 1
.names "spi_intrface_SCK_GEN_CLK_DIVDR/qout<0>".Q "spi_intrface_SCK_GEN_clk_cnt<1>".Q 
       "spi_intrface_SCK_GEN_clk_cnt<2>".Q "spi_intrface_SCK_GEN_clk_cnt<3>".Q 
        "spi_intrface_SCK_GEN_clk_cnt<4>".T
1111 1
.names "spi_intrface_rcv_shift_reg/rcv_bitcnt_int<0>".Q 
       "spi_intrface_rcv_shift_reg/rcv_bitcnt_int<1>".Q 
        "spi_intrface_rcv_shift_reg/rcv_bitcnt_int<2>".T
11 1
.names "N_PZ_723"  "spi_intrface_spi_ctrl_sm_bit_cnt<0>".T
1 1
.names "spi_intrface_spi_ctrl_sm_spi_state_FFd2".Q 
       "spi_intrface_spi_ctrl_sm_spi_state_FFd3".Q "uc_intrface_spitr<1>".Q 
       "spi_intrface_xmit_shift_reg_data_int<0>".Q 
       "spi_intrface_xmit_shift_reg_data_int<1>".Q "N_PZ_665" 
        "spi_intrface_xmit_shift_reg_data_int<1>".T
--0-11 1
--1-01 1
10-01- 1
10-10- 1
.names "spi_intrface_spi_ctrl_sm_spi_state_FFd2".Q 
       "spi_intrface_spi_ctrl_sm_spi_state_FFd3".Q "uc_intrface_spitr<2>".Q 
       "spi_intrface_xmit_shift_reg_data_int<1>".Q 
       "spi_intrface_xmit_shift_reg_data_int<2>".Q "N_PZ_665" 
        "spi_intrface_xmit_shift_reg_data_int<2>".T
--0-11 1
--1-01 1
10-01- 1
10-10- 1
.names "spi_intrface_spi_ctrl_sm_spi_state_FFd2".Q 
       "spi_intrface_spi_ctrl_sm_spi_state_FFd3".Q "uc_intrface_spitr<3>".Q 
       "spi_intrface_xmit_shift_reg_data_int<2>".Q 
       "spi_intrface_xmit_shift_reg_data_int<3>".Q "N_PZ_665" 
        "spi_intrface_xmit_shift_reg_data_int<3>".T
--0-11 1
--1-01 1
10-01- 1
10-10- 1
.names "spi_intrface_spi_ctrl_sm_spi_state_FFd2".Q 
       "spi_intrface_spi_ctrl_sm_spi_state_FFd3".Q "uc_intrface_spitr<4>".Q 
       "spi_intrface_xmit_shift_reg_data_int<3>".Q 
       "spi_intrface_xmit_shift_reg_data_int<4>".Q "N_PZ_665" 
        "spi_intrface_xmit_shift_reg_data_int<4>".T
--0-11 1
--1-01 1
10-01- 1
10-10- 1
.names "spi_intrface_spi_ctrl_sm_spi_state_FFd2".Q 
       "spi_intrface_spi_ctrl_sm_spi_state_FFd3".Q "uc_intrface_spitr<5>".Q 
       "spi_intrface_xmit_shift_reg_data_int<4>".Q 
       "spi_intrface_xmit_shift_reg_data_int<5>".Q "N_PZ_665" 
        "spi_intrface_xmit_shift_reg_data_int<5>".T
--0-11 1
--1-01 1
10-01- 1
10-10- 1
.names "spi_intrface_spi_ctrl_sm_spi_state_FFd2".Q 
       "spi_intrface_spi_ctrl_sm_spi_state_FFd3".Q "uc_intrface_spitr<6>".Q 
       "spi_intrface_xmit_shift_reg_data_int<5>".Q 
       "spi_intrface_xmit_shift_reg_data_int<6>".Q "N_PZ_665" 
        "spi_intrface_xmit_shift_reg_data_int<6>".T
--0-11 1
--1-01 1
10-01- 1
10-10- 1
.names "spi_intrface_spi_ctrl_sm_spi_state_FFd2".Q 
       "spi_intrface_spi_ctrl_sm_spi_state_FFd3".Q "uc_intrface_spitr<7>".Q 
       "spi_intrface_xmit_shift_reg_data_int<6>".Q 
       "spi_intrface_xmit_shift_reg_data_int<7>".Q "N_PZ_665" 
        "spi_intrface_xmit_shift_reg_data_int<7>".T
--0-11 1
--1-01 1
10-01- 1
10-10- 1
.names "spi_intrface_spi_ctrl_sm_bit_cnt<0>".Q "N_PZ_723" 
        "spi_intrface_spi_ctrl_sm_bit_cnt<1>".T
11 1
.names "spi_intrface_spi_ctrl_sm_bit_cnt<0>".Q "spi_intrface_spi_ctrl_sm_bit_cnt<1>".Q 
       "N_PZ_723"  "spi_intrface_spi_ctrl_sm_bit_cnt<2>".T
111 1
.names "spi_intrface_spi_ctrl_sm_bit_cnt<0>".Q "spi_intrface_spi_ctrl_sm_bit_cnt<1>".Q 
       "spi_intrface_spi_ctrl_sm_bit_cnt<2>".Q "N_PZ_723" 
        "spi_intrface_spi_ctrl_sm_bit_cnt<3>".T
1111 1
.names "wr_n" "addr_data<7>".PIN "uc_intrface_spien".Q "uc_intrface_prs_state_FFd2".Q 
       "uc_intrface_prs_state_FFd1".Q "uc_intrface_cntrl_en".Q  "uc_intrface_spien".T
001111 1
010111 1
.names "wr_n" "addr_data<2>".PIN "uc_intrface_prs_state_FFd2".Q 
       "uc_intrface_prs_state_FFd1".Q "uc_intrface_cpha".Q "uc_intrface_cntrl_en".Q 
        "uc_intrface_cpha".T
001111 1
011101 1
.names "wr_n" "addr_data<4>".PIN "uc_intrface_prs_state_FFd2".Q 
       "uc_intrface_prs_state_FFd1".Q "uc_intrface_clkdiv<1>".Q 
       "uc_intrface_cntrl_en".Q  "uc_intrface_clkdiv<1>".T
001111 1
011101 1
.names "wr_n" "addr_data<1>".PIN "uc_intrface_prs_state_FFd2".Q 
       "uc_intrface_prs_state_FFd1".Q "uc_intrface_cpol".Q "uc_intrface_cntrl_en".Q 
        "uc_intrface_cpol".T
001111 1