spi_master.blx

spi总线的vhdl代码

1--01- 1
-0-101 1
--0101 1
.names "clk"  "uc_intrface_prs_state_FFd1".CLK
1 1
.names "reset"  "uc_intrface_prs_state_FFd1".AR
0 1
.names "clk"  "uc_intrface_cpha".CLK
1 1
.names "reset"  "uc_intrface_cpha".AR
0 1
.names "clk"  "uc_intrface_clkdiv<1>".CLK
1 1
.names "reset"  "uc_intrface_clkdiv<1>".AR
0 1
.names "clk"  "uc_intrface_cpol".CLK
1 1
.names "reset"  "uc_intrface_cpol".AR
0 1
.names "clk"  "uc_intrface_start".CLK
1 1
.names "reset"  "uc_intrface_start".AR
0 1
.names "clk"  "uc_intrface_rcv_cpol".CLK
1 1
.names "reset"  "uc_intrface_rcv_cpol".AR
0 1
.names "clk"  "uc_intrface_clkdiv<0>".CLK
1 1
.names "reset"  "uc_intrface_clkdiv<0>".AR
0 1
.names "spi_intrface_sck_1"  "spi_intrface_spi_ctrl_sm_bit_cnt<0>".CLK-
1 1
.names "spi_intrface_spi_ctrl_sm_bit_cnt_reset" 
        "spi_intrface_spi_ctrl_sm_bit_cnt<0>".AR
0 1
.names "spi_intrface_sck_1"  "spi_intrface_spi_ctrl_sm_bit_cnt<1>".CLK-
1 1
.names "spi_intrface_spi_ctrl_sm_bit_cnt_reset" 
        "spi_intrface_spi_ctrl_sm_bit_cnt<1>".AR
0 1
.names "spi_intrface_sck_1"  "spi_intrface_spi_ctrl_sm_bit_cnt<2>".CLK-
1 1
.names "spi_intrface_spi_ctrl_sm_bit_cnt_reset" 
        "spi_intrface_spi_ctrl_sm_bit_cnt<2>".AR
0 1
.names "clk"  "uc_intrface_rcv_full_reset".CLK
1 1
.names "reset"  "uc_intrface_rcv_full_reset".AR
0 1
.names "clk"  "uc_intrface_spierr_reset".CLK
1 1
.names "reset"  "uc_intrface_spierr_reset".AR
0 1
.names "sck".PIN  "rcv_data<1>".CLK
1 1
.names "N_PZ_1007"  "rcv_data<1>".AR
0 1
.names "rcv_data<1>".Q  "rcv_data<2>".D
1 1
.names "sck".PIN  "rcv_data<2>".CLK
1 1
.names "N_PZ_1007"  "rcv_data<2>".AR
0 1
.names "N_PZ_656"  "rcv_data<2>".CE
0 1
.names "rcv_data<2>".Q  "rcv_data<3>".D
1 1
.names "sck".PIN  "rcv_data<3>".CLK
1 1
.names "N_PZ_1007"  "rcv_data<3>".AR
0 1
.names "N_PZ_656"  "rcv_data<3>".CE
0 1
.names "rcv_data<3>".Q  "rcv_data<4>".D
1 1
.names "sck".PIN  "rcv_data<4>".CLK
1 1
.names "N_PZ_1007"  "rcv_data<4>".AR
0 1
.names "N_PZ_656"  "rcv_data<4>".CE
0 1
.names "rcv_data<4>".Q  "rcv_data<5>".D
1 1
.names "sck".PIN  "rcv_data<5>".CLK
1 1
.names "N_PZ_1007"  "rcv_data<5>".AR
0 1
.names "N_PZ_656"  "rcv_data<5>".CE
0 1
.names "rcv_data<5>".Q  "rcv_data<6>".D
1 1
.names "sck".PIN  "rcv_data<6>".CLK
1 1
.names "N_PZ_1007"  "rcv_data<6>".AR
0 1
.names "N_PZ_656"  "rcv_data<6>".CE
0 1
.names "spi_intrface_sck_1"  "spi_intrface_spi_ctrl_sm_bit_cnt<3>".CLK-
1 1
.names "spi_intrface_spi_ctrl_sm_bit_cnt_reset" 
        "spi_intrface_spi_ctrl_sm_bit_cnt<3>".AR
0 1
.names "clk"  "uc_intrface_inten".CLK
1 1
.names "reset"  "uc_intrface_inten".AR
0 1
.names "uc_intrface_spierr_reset".Q  "uc_intrface_spierr".D
1 1
.names "clk"  "uc_intrface_spierr".CLK
1 1
.names "reset"  "uc_intrface_spierr".AR
0 1
.names "N_PZ_990"  "uc_intrface_spierr".CE
0 1
.names "clk"  "uc_intrface_spissr<0>".CLK
1 1
.names "reset"  "uc_intrface_spissr<0>".AR
0 1
.names "clk"  "uc_intrface_spissr<1>".CLK
1 1
.names "reset"  "uc_intrface_spissr<1>".AR
0 1
.names "clk"  "uc_intrface_spissr<2>".CLK
1 1
.names "reset"  "uc_intrface_spissr<2>".AR
0 1
.names "clk"  "uc_intrface_spissr<3>".CLK
1 1
.names "reset"  "uc_intrface_spissr<3>".AR
0 1
.names "clk"  "uc_intrface_spissr<4>".CLK
1 1
.names "reset"  "uc_intrface_spissr<4>".AR
0 1
.names "clk"  "uc_intrface_spissr<5>".CLK
1 1
.names "reset"  "uc_intrface_spissr<5>".AR
0 1
.names "clk"  "uc_intrface_spissr<6>".CLK
1 1
.names "reset"  "uc_intrface_spissr<6>".AR
0 1
.names "clk"  "uc_intrface_spissr<7>".CLK
1 1
.names "reset"  "uc_intrface_spissr<7>".AR
0 1
.names "clk"  "uc_intrface_spitr<0>".CLK
1 1
.names "reset"  "uc_intrface_spitr<0>".AR
0 1
.names "clk"  "uc_intrface_spitr<1>".CLK
1 1
.names "reset"  "uc_intrface_spitr<1>".AR
0 1
.names "clk"  "uc_intrface_spitr<2>".CLK
1 1
.names "reset"  "uc_intrface_spitr<2>".AR
0 1
.names "clk"  "uc_intrface_spitr<3>".CLK
1 1
.names "reset"  "uc_intrface_spitr<3>".AR
0 1
.names "clk"  "uc_intrface_spitr<4>".CLK
1 1
.names "reset"  "uc_intrface_spitr<4>".AR
0 1
.names "clk"  "uc_intrface_spitr<5>".CLK
1 1
.names "reset"  "uc_intrface_spitr<5>".AR
0 1
.names "clk"  "uc_intrface_spitr<6>".CLK
1 1
.names "reset"  "uc_intrface_spitr<6>".AR
0 1
.names "clk"  "uc_intrface_spitr<7>".CLK
1 1
.names "reset"  "uc_intrface_spitr<7>".AR
0 1
.names "clk"  "uc_intrface_xmit_empty_reset".CLK
1 1
.names "reset"  "uc_intrface_xmit_empty_reset".AR
0 1
.names "rcv_data<6>".Q  "rcv_data<7>".D
1 1
.names "sck".PIN  "rcv_data<7>".CLK
1 1
.names "N_PZ_1007"  "rcv_data<7>".AR
0 1
.names "N_PZ_656"  "rcv_data<7>".CE
0 1
.names "spi_intrface_sck_1"  "spi_intrface_xmit_shift_reg_data_int<0>".CLK-
1 1
.names "N_PZ_1007"  "spi_intrface_xmit_shift_reg_data_int<0>".AR
0 1
.names "spi_intrface_sck_1"  "spi_intrface_xmit_shift_reg_data_int<1>".CLK-
1 1
.names "N_PZ_1007"  "spi_intrface_xmit_shift_reg_data_int<1>".AR
0 1
.names "spi_intrface_sck_1"  "spi_intrface_xmit_shift_reg_data_int<2>".CLK-
1 1
.names "N_PZ_1007"  "spi_intrface_xmit_shift_reg_data_int<2>".AR
0 1
.names "spi_intrface_sck_1"  "spi_intrface_xmit_shift_reg_data_int<3>".CLK-
1 1
.names "N_PZ_1007"  "spi_intrface_xmit_shift_reg_data_int<3>".AR
0 1
.names "spi_intrface_sck_1"  "spi_intrface_xmit_shift_reg_data_int<4>".CLK-
1 1
.names "N_PZ_1007"  "spi_intrface_xmit_shift_reg_data_int<4>".AR
0 1
.names "spi_intrface_sck_1"  "spi_intrface_xmit_shift_reg_data_int<5>".CLK-
1 1
.names "N_PZ_1007"  "spi_intrface_xmit_shift_reg_data_int<5>".AR
0 1
.names "spi_intrface_sck_1"  "spi_intrface_xmit_shift_reg_data_int<6>".CLK-
1 1
.names "N_PZ_1007"  "spi_intrface_xmit_shift_reg_data_int<6>".AR
0 1
.names "spi_intrface_sck_1"  "spi_intrface_xmit_shift_reg_data_int<7>".CLK-
1 1
.names "N_PZ_1007"  "spi_intrface_xmit_shift_reg_data_int<7>".AR
0 1
.names "clk"  "uc_intrface_spirr<0>".CLK
1 1
.names "reset"  "uc_intrface_spirr<0>".AR
0 1
.names "clk"  "uc_intrface_spirr<1>".CLK
1 1
.names "reset"  "uc_intrface_spirr<1>".AR
0 1
.names "clk"  "uc_intrface_spirr<2>".CLK
1 1
.names "reset"  "uc_intrface_spirr<2>".AR
0 1
.names "clk"  "uc_intrface_spirr<3>".CLK
1 1
.names "reset"  "uc_intrface_spirr<3>".AR
0 1
.names "clk"  "uc_intrface_spirr<4>".CLK
1 1
.names "reset"  "uc_intrface_spirr<4>".AR
0 1
.names "clk"  "uc_intrface_spirr<5>".CLK
1 1
.names "reset"  "uc_intrface_spirr<5>".AR
0 1
.names "clk"  "uc_intrface_spirr<6>".CLK
1 1
.names "reset"  "uc_intrface_spirr<6>".AR
0 1
.names "clk"  "uc_intrface_spirr<7>".CLK
1 1
.names "reset"  "uc_intrface_spirr<7>".AR
0 1
.names "spi_intrface_sck_1"  "xmit_empty".CLK-
1 1
.names "N_PZ_1008"  "xmit_empty".AR
0 1
.names "psen_n" "ale_n" "addr<5>" "addr<4>" "addr<3>" "addr<2>" "addr<1>" "addr<0>" 
       "addr<7>" "addr<6>" "uc_intrface_address_low<0>".Q 
       "uc_intrface_address_low<1>".Q "uc_intrface_address_low<2>".Q 
       "uc_intrface_address_low<3>".Q "uc_intrface_address_low<4>".Q 
       "uc_intrface_address_low<5>".Q "uc_intrface_address_low<6>".Q 
       "uc_intrface_address_low<7>".Q  "uc_intrface_xmit_en".D
100000000001010001 1
.names "clk"  "uc_intrface_xmit_en".CLK
1 1
.names "reset"  "uc_intrface_xmit_en".AR
0 1
.names "psen_n" "ale_n" "addr<5>" "addr<4>" "addr<3>" "addr<2>" "addr<1>" "addr<0>" 
       "addr<7>" "addr<6>" "uc_intrface_address_low<0>".Q 
       "uc_intrface_address_low<1>".Q "uc_intrface_address_low<2>".Q 
       "uc_intrface_address_low<3>".Q "uc_intrface_address_low<4>".Q 
       "uc_intrface_address_low<5>".Q "uc_intrface_address_low<6>".Q 
       "uc_intrface_address_low<7>".Q  "uc_intrface_rcv_en".D
100000000001110001 1
.names "clk"  "uc_intrface_rcv_en".CLK
1 1
.names "reset"  "uc_intrface_rcv_en".AR
0 1
.names "psen_n" "ale_n" "addr<5>" "addr<4>" "addr<3>" "addr<2>" "addr<1>" "addr<0>" 
       "addr<7>" "addr<6>" "uc_intrface_address_low<0>".Q 
       "uc_intrface_address_low<1>".Q "uc_intrface_address_low<2>".Q 
       "uc_intrface_address_low<3>".Q "uc_intrface_address_low<4>".Q 
       "uc_intrface_address_low<5>".Q "uc_intrface_address_low<6>".Q 
       "uc_intrface_address_low<7>".Q  "uc_intrface_ssel_en".D
100000000000010001 1
.names "clk"  "uc_intrface_ssel_en".CLK
1 1
.names "reset"  "uc_intrface_ssel_en".AR
0 1
.names "psen_n" "ale_n" "addr<5>" "addr<4>" "addr<3>" "addr<2>" "addr<1>" "addr<0>" 
       "addr<7>" "addr<6>" "uc_intrface_address_low<0>".Q 
       "uc_intrface_address_low<1>".Q "uc_intrface_address_low<2>".Q 
       "uc_intrface_address_low<3>".Q "uc_intrface_address_low<4>".Q 
       "uc_intrface_address_low<5>".Q "uc_intrface_address_low<6>".Q 
       "uc_intrface_address_low<7>".Q  "uc_intrface_stat_en".D
100000000000000001 1
.names "clk"  "uc_intrface_stat_en".CLK
1 1
.names "reset"  "uc_intrface_stat_en".AR
0 1
.names "spi_intrface_spi_ctrl_sm_ss_in_neg".Q "spi_intrface_spi_ctrl_sm_ss_in_pos".Q 
        "spi_intrface_spi_ctrl_sm_ss_in_int".D-