spi_master.blx

spi总线的vhdl代码

         "spi_intrface_SCK_GEN_clk_cnt<1>".CLK "spi_intrface_SCK_GEN_clk_cnt<1>".AR 
         "spi_intrface_SCK_GEN_clk_cnt<2>".CLK "spi_intrface_SCK_GEN_clk_cnt<2>".AR 
         "spi_intrface_SCK_GEN_clk_cnt<3>".CLK "spi_intrface_SCK_GEN_clk_cnt<3>".AR 
         "spi_intrface_rcv_shift_reg/rcv_bitcnt_int<1>".CLK 
         "spi_intrface_rcv_shift_reg/rcv_bitcnt_int<1>".AR 
         "spi_intrface_SCK_GEN_CLK_DIVDR/qout<0>".CLK 
         "spi_intrface_SCK_GEN_CLK_DIVDR/qout<0>".AR 
         "spi_intrface_SCK_GEN_clk_cnt<4>".CLK "spi_intrface_SCK_GEN_clk_cnt<4>".AR 
         "spi_intrface_rcv_shift_reg/rcv_bitcnt_int<2>".CLK 
         "spi_intrface_rcv_shift_reg/rcv_bitcnt_int<2>".AR 
         "spi_intrface_SCK_GEN_sck_0".D "spi_intrface_SCK_GEN_sck_0".CLK 
         "spi_intrface_SCK_GEN_sck_0".AR "uc_intrface_address_match".D 
         "uc_intrface_address_match".CLK "uc_intrface_address_match".AR 
         "uc_intrface_cntrl_en".D "uc_intrface_cntrl_en".CLK "uc_intrface_cntrl_en".AR 
         "spi_intrface_rcv_shift_reg/miso_neg".D 
         "spi_intrface_rcv_shift_reg/miso_neg".CLK 
         "spi_intrface_rcv_shift_reg/miso_neg".AR 
         "spi_intrface_rcv_shift_reg/miso_pos".D 
         "spi_intrface_rcv_shift_reg/miso_pos".CLK 
         "spi_intrface_rcv_shift_reg/miso_pos".AR 
         "spi_intrface_spi_ctrl_sm_ss_in_neg".D 
         "spi_intrface_spi_ctrl_sm_ss_in_neg".CLK 
         "spi_intrface_spi_ctrl_sm_ss_in_neg".AP "spi_intrface_spi_ctrl_sm_ss_in_pos".D 
         "spi_intrface_spi_ctrl_sm_ss_in_pos".CLK 
         "spi_intrface_spi_ctrl_sm_ss_in_pos".AP "uc_intrface_bb".D 
         "uc_intrface_bb".CLK "uc_intrface_bb".AR "uc_intrface_dt".D 
         "uc_intrface_dt".CLK "uc_intrface_dt".AR 
         "spi_intrface_rcv_shift_reg/rcv_bitcnt_int<0>".T 
         "spi_intrface_SCK_GEN_CLK_DIVDR/qout<0>".T "spi_intrface_SCK_GEN_clk_cnt<1>".T 
         "spi_intrface_SCK_GEN_clk_cnt<2>".T "spi_intrface_SCK_GEN_clk_cnt<3>".T 
         "spi_intrface_rcv_shift_reg/rcv_bitcnt_int<1>".T 
         "spi_intrface_SCK_GEN_clk_cnt<4>".T 
         "spi_intrface_rcv_shift_reg/rcv_bitcnt_int<2>".T 
         "spi_intrface_spi_ctrl_sm_bit_cnt<0>".T 
         "spi_intrface_xmit_shift_reg_data_int<1>".T 
         "spi_intrface_xmit_shift_reg_data_int<2>".T 
         "spi_intrface_xmit_shift_reg_data_int<3>".T 
         "spi_intrface_xmit_shift_reg_data_int<4>".T 
         "spi_intrface_xmit_shift_reg_data_int<5>".T 
         "spi_intrface_xmit_shift_reg_data_int<6>".T 
         "spi_intrface_xmit_shift_reg_data_int<7>".T 
         "spi_intrface_spi_ctrl_sm_bit_cnt<1>".T 
         "spi_intrface_spi_ctrl_sm_bit_cnt<2>".T 
         "spi_intrface_spi_ctrl_sm_bit_cnt<3>".T "uc_intrface_spien".T 
         "uc_intrface_cpha".T "uc_intrface_clkdiv<1>".T "uc_intrface_cpol".T 
         "uc_intrface_start".T "uc_intrface_rcv_cpol".T "uc_intrface_clkdiv<0>".T 
         "uc_intrface_inten".T "uc_intrface_spissr<0>".T "uc_intrface_spissr<1>".T 
         "uc_intrface_spissr<2>".T "uc_intrface_spissr<3>".T "uc_intrface_spissr<4>".T 
         "uc_intrface_spissr<5>".T "uc_intrface_spissr<6>".T "uc_intrface_spissr<7>".T 
         "uc_intrface_spitr<0>".T "uc_intrface_spitr<1>".T "uc_intrface_spitr<2>".T 
         "uc_intrface_spitr<3>".T "uc_intrface_spitr<4>".T "uc_intrface_spitr<5>".T 
         "uc_intrface_spitr<6>".T "uc_intrface_spitr<7>".T "addr_data<0>".D 
         "addr_data<1>".D "addr_data<2>".D "addr_data<3>".D "addr_data<4>".D 
         "addr_data<5>".D "addr_data<6>".D "addr_data<7>".D "int_n".D "rcv_data<1>".D 
         "spi_intrface_xmit_shift_reg_data_int<0>".D "uc_intrface_spirr<0>".D 
         "uc_intrface_spirr<1>".D "uc_intrface_spirr<2>".D "uc_intrface_spirr<3>".D 
         "uc_intrface_spirr<4>".D "uc_intrface_spirr<5>".D "uc_intrface_spirr<6>".D 
         "uc_intrface_spirr<7>".D "uc_intrface_rcv_full_reset".D 
         "uc_intrface_spierr_reset".D "uc_intrface_xmit_empty_reset".D "xmit_empty".D
.names "uc_intrface_rcv_full_reset".Q "N_PZ_667"  "spi_intrface_spi_ctrl_sm__not0003"
10 1
.names "sck".Q "spi_intrface_spi_ctrl_sm_spi_state_FFd2".Q 
       "spi_intrface_spi_ctrl_sm_spi_state_FFd3".Q "uc_intrface_cpha".Q 
       "uc_intrface_cpol".Q "spi_intrface_SCK_GEN_sck_int".Q 
       "spi_intrface_SCK_GEN_sck_d1".Q "N_PZ_723"  "spi_intrface_sck_1"
-----0-- 1
-0-----0 1
--1----0 1
01100-1- 1
11101-0- 1
.names "spi_intrface_spi_ctrl_sm_ss_in_int".Q "N_PZ_723" 
        "spi_intrface_spi_ctrl_sm_bit_cnt_reset"
11 1
.names "uc_intrface_spien".Q "N_PZ_656"  "spi_intrface_rcv_shift_reg/_or0000"
10 1
.names "clk"  "addr_data<0>".CLK
1 1
.names "reset"  "addr_data<0>".AR
0 1
.names "rd_n" "uc_intrface_prs_state_FFd2".Q "uc_intrface_prs_state_FFd1".Q 
        "addr_data<0>".OE
011 1
.names "clk"  "addr_data<1>".CLK
1 1
.names "reset"  "addr_data<1>".AR
0 1
.names "rd_n" "uc_intrface_prs_state_FFd2".Q "uc_intrface_prs_state_FFd1".Q 
        "addr_data<1>".OE
011 1
.names "clk"  "addr_data<2>".CLK
1 1
.names "reset"  "addr_data<2>".AR
0 1
.names "rd_n" "uc_intrface_prs_state_FFd2".Q "uc_intrface_prs_state_FFd1".Q 
        "addr_data<2>".OE
011 1
.names "clk"  "addr_data<3>".CLK
1 1
.names "reset"  "addr_data<3>".AR
0 1
.names "rd_n" "uc_intrface_prs_state_FFd2".Q "uc_intrface_prs_state_FFd1".Q 
        "addr_data<3>".OE
011 1
.names "clk"  "addr_data<4>".CLK
1 1
.names "reset"  "addr_data<4>".AR
0 1
.names "rd_n" "uc_intrface_prs_state_FFd2".Q "uc_intrface_prs_state_FFd1".Q 
        "addr_data<4>".OE
011 1
.names "clk"  "addr_data<5>".CLK
1 1
.names "reset"  "addr_data<5>".AR
0 1
.names "rd_n" "uc_intrface_prs_state_FFd2".Q "uc_intrface_prs_state_FFd1".Q 
        "addr_data<5>".OE
011 1
.names "clk"  "addr_data<6>".CLK
1 1
.names "reset"  "addr_data<6>".AR
0 1
.names "rd_n" "uc_intrface_prs_state_FFd2".Q "uc_intrface_prs_state_FFd1".Q 
        "addr_data<6>".OE
011 1
.names "clk"  "addr_data<7>".CLK
1 1
.names "reset"  "addr_data<7>".AR
0 1
.names "rd_n" "uc_intrface_prs_state_FFd2".Q "uc_intrface_prs_state_FFd1".Q 
        "addr_data<7>".OE
011 1
.names "uc_intrface_cpol".Q  "sck".D.X1
1 1
.names "spi_intrface_sck_1" "uc_intrface_cpha".Q "spi_intrface_SCK_GEN_sck_0".Q 
        "sck".D.X2-
11- 1
-00 1
.names "clk"  "sck".CLK
1 1
.names "uc_intrface_spien".Q  "sck".AR
0 1
.names "spi_intrface_spi_ctrl_sm_ss_in_int".Q  "sck".OE
1 1
.names "uc_intrface_spissr<0>".Q "N_PZ_656"  "ss_n<0>".D-
10 1
.names "clk"  "ss_n<0>".CLK-
1 1
.names "uc_intrface_spien".Q  "ss_n<0>".AP
0 1
.names "spi_intrface_spi_ctrl_sm_ss_in_int".Q  "ss_n<0>".OE
1 1
.names "uc_intrface_spissr<1>".Q "N_PZ_656"  "ss_n<1>".D-
10 1
.names "clk"  "ss_n<1>".CLK-
1 1
.names "uc_intrface_spien".Q  "ss_n<1>".AP
0 1
.names "spi_intrface_spi_ctrl_sm_ss_in_int".Q  "ss_n<1>".OE
1 1
.names "uc_intrface_spissr<2>".Q "N_PZ_656"  "ss_n<2>".D-
10 1
.names "clk"  "ss_n<2>".CLK-
1 1
.names "uc_intrface_spien".Q  "ss_n<2>".AP
0 1
.names "spi_intrface_spi_ctrl_sm_ss_in_int".Q  "ss_n<2>".OE
1 1
.names "uc_intrface_spissr<3>".Q "N_PZ_656"  "ss_n<3>".D-
10 1
.names "clk"  "ss_n<3>".CLK-
1 1
.names "uc_intrface_spien".Q  "ss_n<3>".AP
0 1
.names "spi_intrface_spi_ctrl_sm_ss_in_int".Q  "ss_n<3>".OE
1 1
.names "uc_intrface_spissr<4>".Q "N_PZ_656"  "ss_n<4>".D-
10 1
.names "clk"  "ss_n<4>".CLK-
1 1
.names "uc_intrface_spien".Q  "ss_n<4>".AP
0 1
.names "spi_intrface_spi_ctrl_sm_ss_in_int".Q  "ss_n<4>".OE
1 1
.names "uc_intrface_spissr<5>".Q "N_PZ_656"  "ss_n<5>".D-
10 1
.names "clk"  "ss_n<5>".CLK-
1 1
.names "uc_intrface_spien".Q  "ss_n<5>".AP
0 1
.names "spi_intrface_spi_ctrl_sm_ss_in_int".Q  "ss_n<5>".OE
1 1
.names "uc_intrface_spissr<6>".Q "N_PZ_656"  "ss_n<6>".D-
10 1
.names "clk"  "ss_n<6>".CLK-
1 1
.names "uc_intrface_spien".Q  "ss_n<6>".AP
0 1
.names "spi_intrface_spi_ctrl_sm_ss_in_int".Q  "ss_n<6>".OE
1 1
.names "uc_intrface_spissr<7>".Q "N_PZ_656"  "ss_n<7>".D-
10 1
.names "clk"  "ss_n<7>".CLK-
1 1
.names "uc_intrface_spien".Q  "ss_n<7>".AP
0 1
.names "spi_intrface_spi_ctrl_sm_ss_in_int".Q  "ss_n<7>".OE
1 1
.names "uc_intrface_rcv_full_reset".Q  "rcv_full".D
1 1
.names "clk"  "rcv_full".CLK
1 1
.names "uc_intrface_spien".Q  "rcv_full".AR
0 1
.names "spi_intrface_spi_ctrl_sm__not0003"  "rcv_full".CE
0 1
.names "clk"  "int_n".CLK
1 1
.names "reset"  "int_n".AP
0 1
.names "spi_intrface_xmit_shift_reg_data_int<7>".Q  "mosi".D
1 1
.names "clk"  "mosi".CLK
1 1
.names "uc_intrface_spien".Q  "mosi".AR
0 1
.names "spi_intrface_spi_ctrl_sm_ss_in_int".Q  "mosi".OE
1 1
.names "clk"  "uc_intrface_spien".CLK
1 1
.names "reset"  "uc_intrface_spien".AR
0 1
.names "xmit_empty".Q "sck".Q "spi_intrface_spi_ctrl_sm_spi_state_FFd4".Q 
       "spi_intrface_spi_ctrl_sm_spi_state_FFd2".Q 
       "spi_intrface_spi_ctrl_sm_spi_state_FFd3".Q 
       "spi_intrface_spi_ctrl_sm_spi_state_FFd1".Q "uc_intrface_cpha".Q 
       "uc_intrface_cpol".Q "uc_intrface_start".Q 
       "spi_intrface_spi_ctrl_sm_bit_cnt<0>".Q "spi_intrface_SCK_GEN_sck_int".Q 
       "spi_intrface_SCK_GEN_sck_d1".Q "spi_intrface_SCK_GEN_sck_int_d1".Q 
       "spi_intrface_spi_ctrl_sm_bit_cnt<1>".Q "spi_intrface_spi_ctrl_sm_bit_cnt<2>".Q 
       "spi_intrface_spi_ctrl_sm_bit_cnt<3>".Q 
        "spi_intrface_spi_ctrl_sm_spi_state_FFd4".T
--1110---------- 1
--11------0-1--- 1
----01----0-1--- 1
--10-0----1-0--- 1
0-0000--1------- 1
0-011-1-1------- 1
-0011--0---1---- 1
-1011--1---0---- 1
--0010----0-1--- 1
--010----0---001 1
.names "clk"  "spi_intrface_spi_ctrl_sm_spi_state_FFd4".CLK
1 1
.names "N_PZ_1007"  "spi_intrface_spi_ctrl_sm_spi_state_FFd4".AR
0 1
.names "spi_intrface_spi_ctrl_sm_spi_state_FFd4".Q 
       "spi_intrface_spi_ctrl_sm_spi_state_FFd2".Q 
       "spi_intrface_spi_ctrl_sm_spi_state_FFd3".Q "spi_intrface_SCK_GEN_sck_int".Q 
       "spi_intrface_SCK_GEN_sck_int_d1".Q "N_PZ_665" 
        "spi_intrface_spi_ctrl_sm_spi_state_FFd2".T
-1---1 1
111--- 1
10110- 1
.names "clk"  "spi_intrface_spi_ctrl_sm_spi_state_FFd2".CLK
1 1
.names "N_PZ_1007"  "spi_intrface_spi_ctrl_sm_spi_state_FFd2".AR
0 1
.names "spi_intrface_spi_ctrl_sm_spi_state_FFd4".Q 
       "spi_intrface_spi_ctrl_sm_spi_state_FFd2".Q 
       "spi_intrface_spi_ctrl_sm_spi_state_FFd3".Q 
       "spi_intrface_spi_ctrl_sm_spi_state_FFd1".Q "spi_intrface_SCK_GEN_sck_int".Q 
       "spi_intrface_SCK_GEN_sck_int_d1".Q  "spi_intrface_spi_ctrl_sm_spi_state_FFd3".T
1110-- 1
1-0101 1
11-001 1
10-010 1
001101 1
.names "clk"  "spi_intrface_spi_ctrl_sm_spi_state_FFd3".CLK
1 1
.names "N_PZ_1007"  "spi_intrface_spi_ctrl_sm_spi_state_FFd3".AR
0 1
.names "spi_intrface_spi_ctrl_sm_spi_state_FFd4".Q 
       "spi_intrface_spi_ctrl_sm_spi_state_FFd2".Q 
       "spi_intrface_spi_ctrl_sm_spi_state_FFd3".Q 
       "spi_intrface_spi_ctrl_sm_spi_state_FFd1".Q "spi_intrface_SCK_GEN_sck_int".Q 
       "spi_intrface_SCK_GEN_sck_int_d1".Q  "spi_intrface_spi_ctrl_sm_spi_state_FFd1".T
1110-- 1
0-1101 1
.names "clk"  "spi_intrface_spi_ctrl_sm_spi_state_FFd1".CLK
1 1
.names "N_PZ_1007"  "spi_intrface_spi_ctrl_sm_spi_state_FFd1".AR
0 1
.names "psen_n" "ale_n" "wr_n" "rd_n" "uc_intrface_prs_state_FFd2".Q 
       "uc_intrface_prs_state_FFd1".Q "uc_intrface_address_match".Q 
        "uc_intrface_prs_state_FFd2".T
----100 1
--1111- 1
10--00- 1
.names "clk"  "uc_intrface_prs_state_FFd2".CLK
1 1
.names "reset"  "uc_intrface_prs_state_FFd2".AR
0 1
.names "ale_n" "wr_n" "rd_n" "uc_intrface_prs_state_FFd2".Q 
       "uc_intrface_prs_state_FFd1".Q "uc_intrface_address_match".Q 
        "uc_intrface_prs_state_FFd1".T