📄 spi_master.blx
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# XPLAOPT Version 9.99.99.99
# XPLAOPT -run s -it b -i spi_master.blx -dev XA2C64A-7VQ100 -reg -xor a -mode
# 1 -th 28 -fi 32 -bfi 38 -pre keep -unused keeper -terminate keeper -no_output_files
#$ MODULE spi_master
#$ PINS 6 "addr<0>" "addr<1>" "addr<2>" "addr<3>" "addr<4>" "addr<5>"
#$ PINS 5 "addr<6>" "addr<7>" "addr_data<0>" "addr_data<1>" "addr_data<2>"
#$ PINS 4 "addr_data<3>" "addr_data<4>" "addr_data<5>" "addr_data<6>"
#$ PINS 7 "addr_data<7>" "ale_n" "clk" "int_n" "miso" "mosi" "psen_n"
#$ PINS 7 "rcv_full" "rd_n" "reset" "sck" "ss_in_n" "ss_n<0>" "ss_n<1>"
#$ PINS 7 "ss_n<2>" "ss_n<3>" "ss_n<4>" "ss_n<5>" "ss_n<6>" "ss_n<7>" "wr_n"
#$ PINS 1 "xmit_empty"
#$ NODES 4 "N_PZ_1007"'co' "N_PZ_1008"'co' "N_PZ_656"'co' "N_PZ_665"'co'
#$ NODES 4 "N_PZ_667"'co' "N_PZ_720"'co' "N_PZ_723"'co' "N_PZ_990"'co'
#$ NODES 4 "rcv_data<1>" "rcv_data<2>" "rcv_data<3>" "rcv_data<4>"
#$ NODES 3 "rcv_data<5>" "rcv_data<6>" "rcv_data<7>"
#$ NODES 1 "spi_intrface_SCK_GEN_CLK_DIVDR/qout<0>"
#$ NODES 1 "spi_intrface_SCK_GEN_clk_cnt<1>"
#$ NODES 1 "spi_intrface_SCK_GEN_clk_cnt<2>"
#$ NODES 1 "spi_intrface_SCK_GEN_clk_cnt<3>"
#$ NODES 2 "spi_intrface_SCK_GEN_clk_cnt<4>" "spi_intrface_SCK_GEN_sck_0"
#$ NODES 2 "spi_intrface_SCK_GEN_sck_d1" "spi_intrface_SCK_GEN_sck_int"
#$ NODES 1 "spi_intrface_SCK_GEN_sck_int_d1"
#$ NODES 1 "spi_intrface_rcv_shift_reg/_or0000"
#$ NODES 1 "spi_intrface_rcv_shift_reg/miso_neg"
#$ NODES 1 "spi_intrface_rcv_shift_reg/miso_pos"
#$ NODES 1 "spi_intrface_rcv_shift_reg/rcv_bitcnt_int<0>"
#$ NODES 1 "spi_intrface_rcv_shift_reg/rcv_bitcnt_int<1>"
#$ NODES 1 "spi_intrface_rcv_shift_reg/rcv_bitcnt_int<2>"
#$ NODES 2 "spi_intrface_sck_1" "spi_intrface_spi_ctrl_sm__not0003"
#$ NODES 1 "spi_intrface_spi_ctrl_sm_bit_cnt<0>"
#$ NODES 1 "spi_intrface_spi_ctrl_sm_bit_cnt<1>"
#$ NODES 1 "spi_intrface_spi_ctrl_sm_bit_cnt<2>"
#$ NODES 1 "spi_intrface_spi_ctrl_sm_bit_cnt<3>"
#$ NODES 1 "spi_intrface_spi_ctrl_sm_bit_cnt_reset"
#$ NODES 1 "spi_intrface_spi_ctrl_sm_spi_state_FFd1"
#$ NODES 1 "spi_intrface_spi_ctrl_sm_spi_state_FFd2"
#$ NODES 1 "spi_intrface_spi_ctrl_sm_spi_state_FFd3"
#$ NODES 1 "spi_intrface_spi_ctrl_sm_spi_state_FFd4"
#$ NODES 1 "spi_intrface_spi_ctrl_sm_ss_in_int"
#$ NODES 1 "spi_intrface_spi_ctrl_sm_ss_in_neg"
#$ NODES 1 "spi_intrface_spi_ctrl_sm_ss_in_pos"
#$ NODES 1 "spi_intrface_xmit_shift_reg_data_int<0>"
#$ NODES 1 "spi_intrface_xmit_shift_reg_data_int<1>"
#$ NODES 1 "spi_intrface_xmit_shift_reg_data_int<2>"
#$ NODES 1 "spi_intrface_xmit_shift_reg_data_int<3>"
#$ NODES 1 "spi_intrface_xmit_shift_reg_data_int<4>"
#$ NODES 1 "spi_intrface_xmit_shift_reg_data_int<5>"
#$ NODES 1 "spi_intrface_xmit_shift_reg_data_int<6>"
#$ NODES 1 "spi_intrface_xmit_shift_reg_data_int<7>"
#$ NODES 2 "uc_intrface_address_low<0>" "uc_intrface_address_low<1>"
#$ NODES 2 "uc_intrface_address_low<2>" "uc_intrface_address_low<3>"
#$ NODES 2 "uc_intrface_address_low<4>" "uc_intrface_address_low<5>"
#$ NODES 2 "uc_intrface_address_low<6>" "uc_intrface_address_low<7>"
#$ NODES 2 "uc_intrface_address_match" "uc_intrface_bb"
#$ NODES 2 "uc_intrface_clkdiv<0>" "uc_intrface_clkdiv<1>"
#$ NODES 3 "uc_intrface_cntrl_en" "uc_intrface_cpha" "uc_intrface_cpol"
#$ NODES 3 "uc_intrface_dt" "uc_intrface_inten" "uc_intrface_prs_state_FFd1"
#$ NODES 2 "uc_intrface_prs_state_FFd2" "uc_intrface_rcv_cpol"
#$ NODES 2 "uc_intrface_rcv_en" "uc_intrface_rcv_full_reset"
#$ NODES 2 "uc_intrface_spien" "uc_intrface_spierr"
#$ NODES 2 "uc_intrface_spierr_reset" "uc_intrface_spirr<0>"
#$ NODES 2 "uc_intrface_spirr<1>" "uc_intrface_spirr<2>"
#$ NODES 2 "uc_intrface_spirr<3>" "uc_intrface_spirr<4>"
#$ NODES 2 "uc_intrface_spirr<5>" "uc_intrface_spirr<6>"
#$ NODES 2 "uc_intrface_spirr<7>" "uc_intrface_spissr<0>"
#$ NODES 2 "uc_intrface_spissr<1>" "uc_intrface_spissr<2>"
#$ NODES 2 "uc_intrface_spissr<3>" "uc_intrface_spissr<4>"
#$ NODES 2 "uc_intrface_spissr<5>" "uc_intrface_spissr<6>"
#$ NODES 2 "uc_intrface_spissr<7>" "uc_intrface_spitr<0>"
#$ NODES 2 "uc_intrface_spitr<1>" "uc_intrface_spitr<2>"
#$ NODES 2 "uc_intrface_spitr<3>" "uc_intrface_spitr<4>"
#$ NODES 2 "uc_intrface_spitr<5>" "uc_intrface_spitr<6>"
#$ NODES 3 "uc_intrface_spitr<7>" "uc_intrface_ssel_en" "uc_intrface_start"
#$ NODES 2 "uc_intrface_stat_en" "uc_intrface_xmit_empty_reset"
#$ NODES 1 "uc_intrface_xmit_en"
#$ PROPERTY xpla USER_SLEW_RATE addr_data<0> addr_data<1> addr_data<2>
#$ PROPERTY xpla USER_SLEW_RATE addr_data<3> addr_data<4> addr_data<5>
#$ PROPERTY xpla USER_SLEW_RATE addr_data<6> addr_data<7> int_n
#$ PROPERTY xpla USER_SLEW_RATE mosi rcv_full sck ss_n<0> ss_n<1>
#$ PROPERTY xpla USER_SLEW_RATE ss_n<2> ss_n<3> ss_n<4> ss_n<5>
#$ PROPERTY xpla USER_SLEW_RATE ss_n<6> ss_n<7> xmit_empty
#$ PROPERTY xpla KEEP_TFF spi_intrface_spi_ctrl_sm_spi_state_FFd1
#$ PROPERTY xpla KEEP_TFF spi_intrface_spi_ctrl_sm_spi_state_FFd2
#$ PROPERTY xpla KEEP_TFF spi_intrface_spi_ctrl_sm_spi_state_FFd3
#$ PROPERTY xpla KEEP_TFF spi_intrface_spi_ctrl_sm_spi_state_FFd4
#$ PROPERTY xpla KEEP_TFF uc_intrface_prs_state_FFd1 uc_intrface_prs_state_FFd2
#$ PROPERTY xpla TERMINATE_KEEPER addr_data<0> addr_data<1> addr_data<2>
#$ PROPERTY xpla TERMINATE_KEEPER addr_data<3> addr_data<4> addr_data<5>
#$ PROPERTY xpla TERMINATE_KEEPER addr_data<6> addr_data<7> mosi
#$ PROPERTY xpla TERMINATE_KEEPER sck ss_n<0> ss_n<1> ss_n<2>
#$ PROPERTY xpla TERMINATE_KEEPER ss_n<3> ss_n<4> ss_n<5> ss_n<6>
#$ PROPERTY xpla TERMINATE_KEEPER ss_n<7>
#$ PROPERTY xpla POWER_UP_HIGH ss_n<0> ss_n<1> ss_n<2> ss_n<3>
#$ PROPERTY xpla POWER_UP_HIGH ss_n<4> ss_n<5> ss_n<6> ss_n<7>
#$ PROPERTY xpla POWER_UP_HIGH spi_intrface_spi_ctrl_sm_ss_in_int
#$ PROPERTY xpla POWER_UP_HIGH spi_intrface_spi_ctrl_sm_ss_in_neg
#$ PROPERTY xpla POWER_UP_HIGH spi_intrface_spi_ctrl_sm_ss_in_pos
#$ PROPERTY xpla unused_keeper
#$ PROPERTY xpla IOSTD addr<0> 2 -1
#$ PROPERTY xpla IOSTD addr<1> 2 -1
#$ PROPERTY xpla IOSTD addr<2> 2 -1
#$ PROPERTY xpla IOSTD addr<3> 2 -1
#$ PROPERTY xpla IOSTD addr<4> 2 -1
#$ PROPERTY xpla IOSTD addr<5> 2 -1
#$ PROPERTY xpla IOSTD addr<6> 2 -1
#$ PROPERTY xpla IOSTD addr<7> 2 -1
#$ PROPERTY xpla IOSTD addr_data<0> 2 -1
#$ PROPERTY xpla IOSTD addr_data<1> 2 -1
#$ PROPERTY xpla IOSTD addr_data<2> 2 -1
#$ PROPERTY xpla IOSTD addr_data<3> 2 -1
#$ PROPERTY xpla IOSTD addr_data<4> 2 -1
#$ PROPERTY xpla IOSTD addr_data<5> 2 -1
#$ PROPERTY xpla IOSTD addr_data<6> 2 -1
#$ PROPERTY xpla IOSTD addr_data<7> 2 -1
#$ PROPERTY xpla IOSTD ale_n 2 -1
#$ PROPERTY xpla IOSTD clk 2 -1
#$ PROPERTY xpla IOSTD int_n 2 -1
#$ PROPERTY xpla IOSTD miso 2 -1
#$ PROPERTY xpla IOSTD mosi 2 -1
#$ PROPERTY xpla IOSTD psen_n 2 -1
#$ PROPERTY xpla IOSTD rcv_full 2 -1
#$ PROPERTY xpla IOSTD rd_n 2 -1
#$ PROPERTY xpla IOSTD reset 2 -1
#$ PROPERTY xpla IOSTD sck 2 -1
#$ PROPERTY xpla IOSTD ss_in_n 2 -1
#$ PROPERTY xpla IOSTD ss_n<0> 2 -1
#$ PROPERTY xpla IOSTD ss_n<1> 2 -1
#$ PROPERTY xpla IOSTD ss_n<2> 2 -1
#$ PROPERTY xpla IOSTD ss_n<3> 2 -1
#$ PROPERTY xpla IOSTD ss_n<4> 2 -1
#$ PROPERTY xpla IOSTD ss_n<5> 2 -1
#$ PROPERTY xpla IOSTD ss_n<6> 2 -1
#$ PROPERTY xpla IOSTD ss_n<7> 2 -1
#$ PROPERTY xpla IOSTD wr_n 2 -1
#$ PROPERTY xpla IOSTD xmit_empty 2 -1
.model spi_master
.inputs "psen_n" "ale_n" "addr<5>" "addr<4>" "addr<3>" "addr<2>" "addr<1>" "addr<0>"
"clk" "reset" "wr_n" "addr_data<7>".PIN "addr_data<2>".PIN "addr_data<4>".PIN
"addr_data<1>".PIN "addr_data<5>".PIN "addr_data<0>".PIN "addr_data<3>".PIN
"sck".PIN "addr_data<6>".PIN "xmit_empty".Q "rd_n" "sck".Q "miso" "ss_in_n"
"addr<7>" "addr<6>" "rcv_full".Q "int_n".Q "uc_intrface_spien".Q
"spi_intrface_spi_ctrl_sm_spi_state_FFd4".Q
"spi_intrface_spi_ctrl_sm_spi_state_FFd2".Q
"spi_intrface_spi_ctrl_sm_spi_state_FFd3".Q
"spi_intrface_spi_ctrl_sm_spi_state_FFd1".Q "uc_intrface_prs_state_FFd2".Q
"uc_intrface_prs_state_FFd1".Q "uc_intrface_cpha".Q "uc_intrface_clkdiv<1>".Q
"uc_intrface_cpol".Q "uc_intrface_start".Q "uc_intrface_rcv_cpol".Q
"uc_intrface_clkdiv<0>".Q "spi_intrface_spi_ctrl_sm_bit_cnt<0>".Q
"uc_intrface_rcv_full_reset".Q "uc_intrface_spierr_reset".Q "rcv_data<1>".Q
"rcv_data<2>".Q "rcv_data<3>".Q "rcv_data<4>".Q "rcv_data<5>".Q
"rcv_data<6>".Q "uc_intrface_inten".Q "uc_intrface_spierr".Q
"uc_intrface_spissr<0>".Q "uc_intrface_spissr<1>".Q "uc_intrface_spissr<2>".Q
"uc_intrface_spissr<3>".Q "uc_intrface_spissr<4>".Q "uc_intrface_spissr<5>".Q
"uc_intrface_spissr<6>".Q "uc_intrface_spissr<7>".Q "uc_intrface_spitr<0>".Q
"uc_intrface_spitr<1>".Q "uc_intrface_spitr<2>".Q "uc_intrface_spitr<3>".Q
"uc_intrface_spitr<4>".Q "uc_intrface_spitr<5>".Q "uc_intrface_spitr<6>".Q
"uc_intrface_spitr<7>".Q "uc_intrface_xmit_empty_reset".Q "rcv_data<7>".Q
"spi_intrface_xmit_shift_reg_data_int<0>".Q
"spi_intrface_xmit_shift_reg_data_int<1>".Q
"spi_intrface_xmit_shift_reg_data_int<2>".Q
"spi_intrface_xmit_shift_reg_data_int<3>".Q
"spi_intrface_xmit_shift_reg_data_int<4>".Q
"spi_intrface_xmit_shift_reg_data_int<5>".Q
"spi_intrface_xmit_shift_reg_data_int<6>".Q
"spi_intrface_xmit_shift_reg_data_int<7>".Q "uc_intrface_spirr<0>".Q
"uc_intrface_spirr<1>".Q "uc_intrface_spirr<2>".Q "uc_intrface_spirr<3>".Q
"uc_intrface_spirr<4>".Q "uc_intrface_spirr<5>".Q "uc_intrface_spirr<6>".Q
"uc_intrface_spirr<7>".Q "uc_intrface_xmit_en".Q "uc_intrface_rcv_en".Q
"uc_intrface_ssel_en".Q "uc_intrface_stat_en".Q
"spi_intrface_spi_ctrl_sm_ss_in_int".Q "spi_intrface_SCK_GEN_sck_int".Q
"spi_intrface_SCK_GEN_sck_d1".Q "spi_intrface_SCK_GEN_sck_int_d1".Q
"spi_intrface_rcv_shift_reg/rcv_bitcnt_int<0>".Q
"uc_intrface_address_low<0>".Q "uc_intrface_address_low<1>".Q
"uc_intrface_address_low<2>".Q "uc_intrface_address_low<3>".Q
"uc_intrface_address_low<4>".Q "uc_intrface_address_low<5>".Q
"uc_intrface_address_low<6>".Q "uc_intrface_address_low<7>".Q
"spi_intrface_SCK_GEN_CLK_DIVDR/qout<0>".Q "spi_intrface_SCK_GEN_sck_0".Q
"uc_intrface_address_match".Q "uc_intrface_cntrl_en".Q
"spi_intrface_rcv_shift_reg/miso_neg".Q
"spi_intrface_rcv_shift_reg/miso_pos".Q "spi_intrface_spi_ctrl_sm_ss_in_neg".Q
"spi_intrface_spi_ctrl_sm_ss_in_pos".Q "uc_intrface_bb".Q "uc_intrface_dt".Q
"spi_intrface_spi_ctrl_sm_bit_cnt<1>".Q
"spi_intrface_spi_ctrl_sm_bit_cnt<2>".Q
"spi_intrface_spi_ctrl_sm_bit_cnt<3>".Q "spi_intrface_SCK_GEN_clk_cnt<1>".Q
"spi_intrface_SCK_GEN_clk_cnt<2>".Q "spi_intrface_SCK_GEN_clk_cnt<3>".Q
"spi_intrface_rcv_shift_reg/rcv_bitcnt_int<1>".Q
"spi_intrface_SCK_GEN_clk_cnt<4>".Q
"spi_intrface_rcv_shift_reg/rcv_bitcnt_int<2>".Q "addr_data<0>".Q
"addr_data<1>".Q "addr_data<2>".Q "addr_data<3>".Q "addr_data<4>".Q
"addr_data<5>".Q "addr_data<6>".Q "addr_data<7>".Q
.outputs "addr_data<0>".CLK "addr_data<0>".AR "addr_data<0>".OE "addr_data<1>".CLK
"addr_data<1>".AR "addr_data<1>".OE "addr_data<2>".CLK "addr_data<2>".AR
"addr_data<2>".OE "addr_data<3>".CLK "addr_data<3>".AR "addr_data<3>".OE
"addr_data<4>".CLK "addr_data<4>".AR "addr_data<4>".OE "addr_data<5>".CLK
"addr_data<5>".AR "addr_data<5>".OE "addr_data<6>".CLK "addr_data<6>".AR
"addr_data<6>".OE "addr_data<7>".CLK "addr_data<7>".AR "addr_data<7>".OE
"sck".D.X1 "sck".D.X2 "sck".CLK "sck".AR "sck".OE "ss_n<0>".D "ss_n<0>".CLK
"ss_n<0>".AP "ss_n<0>".OE "ss_n<1>".D "ss_n<1>".CLK "ss_n<1>".AP "ss_n<1>".OE
"ss_n<2>".D "ss_n<2>".CLK "ss_n<2>".AP "ss_n<2>".OE "ss_n<3>".D "ss_n<3>".CLK
"ss_n<3>".AP "ss_n<3>".OE "ss_n<4>".D "ss_n<4>".CLK "ss_n<4>".AP "ss_n<4>".OE
"ss_n<5>".D "ss_n<5>".CLK "ss_n<5>".AP "ss_n<5>".OE "ss_n<6>".D "ss_n<6>".CLK
"ss_n<6>".AP "ss_n<6>".OE "ss_n<7>".D "ss_n<7>".CLK "ss_n<7>".AP "ss_n<7>".OE
"rcv_full".D "rcv_full".CLK "rcv_full".AR "rcv_full".CE "int_n".CLK "int_n".AP
"mosi".D "mosi".CLK "mosi".AR "mosi".OE "uc_intrface_spien".CLK
"uc_intrface_spien".AR "spi_intrface_spi_ctrl_sm_spi_state_FFd4".T
"spi_intrface_spi_ctrl_sm_spi_state_FFd4".CLK
"spi_intrface_spi_ctrl_sm_spi_state_FFd4".AR
"spi_intrface_spi_ctrl_sm_spi_state_FFd2".T
"spi_intrface_spi_ctrl_sm_spi_state_FFd2".CLK
"spi_intrface_spi_ctrl_sm_spi_state_FFd2".AR
"spi_intrface_spi_ctrl_sm_spi_state_FFd3".T
"spi_intrface_spi_ctrl_sm_spi_state_FFd3".CLK
"spi_intrface_spi_ctrl_sm_spi_state_FFd3".AR
"spi_intrface_spi_ctrl_sm_spi_state_FFd1".T
"spi_intrface_spi_ctrl_sm_spi_state_FFd1".CLK
"spi_intrface_spi_ctrl_sm_spi_state_FFd1".AR "uc_intrface_prs_state_FFd2".T
"uc_intrface_prs_state_FFd2".CLK "uc_intrface_prs_state_FFd2".AR
"uc_intrface_prs_state_FFd1".T "uc_intrface_prs_state_FFd1".CLK
"uc_intrface_prs_state_FFd1".AR "uc_intrface_cpha".CLK "uc_intrface_cpha".AR
"uc_intrface_clkdiv<1>".CLK "uc_intrface_clkdiv<1>".AR "uc_intrface_cpol".CLK
"uc_intrface_cpol".AR "uc_intrface_start".CLK "uc_intrface_start".AR
"uc_intrface_rcv_cpol".CLK "uc_intrface_rcv_cpol".AR
"uc_intrface_clkdiv<0>".CLK "uc_intrface_clkdiv<0>".AR
"spi_intrface_spi_ctrl_sm_bit_cnt<0>".CLK
"spi_intrface_spi_ctrl_sm_bit_cnt<0>".AR
"spi_intrface_spi_ctrl_sm_bit_cnt<1>".CLK
"spi_intrface_spi_ctrl_sm_bit_cnt<1>".AR
"spi_intrface_spi_ctrl_sm_bit_cnt<2>".CLK
"spi_intrface_spi_ctrl_sm_bit_cnt<2>".AR "uc_intrface_rcv_full_reset".CLK
"uc_intrface_rcv_full_reset".AR "uc_intrface_spierr_reset".CLK
"uc_intrface_spierr_reset".AR "rcv_data<1>".CLK "rcv_data<1>".AR
"rcv_data<2>".D "rcv_data<2>".CLK "rcv_data<2>".AR "rcv_data<2>".CE
"rcv_data<3>".D "rcv_data<3>".CLK "rcv_data<3>".AR "rcv_data<3>".CE
"rcv_data<4>".D "rcv_data<4>".CLK "rcv_data<4>".AR "rcv_data<4>".CE
"rcv_data<5>".D "rcv_data<5>".CLK "rcv_data<5>".AR "rcv_data<5>".CE
"rcv_data<6>".D "rcv_data<6>".CLK "rcv_data<6>".AR "rcv_data<6>".CE
"spi_intrface_spi_ctrl_sm_bit_cnt<3>".CLK
"spi_intrface_spi_ctrl_sm_bit_cnt<3>".AR "uc_intrface_inten".CLK
"uc_intrface_inten".AR "uc_intrface_spierr".D "uc_intrface_spierr".CLK
"uc_intrface_spierr".AR "uc_intrface_spierr".CE "uc_intrface_spissr<0>".CLK
"uc_intrface_spissr<0>".AR "uc_intrface_spissr<1>".CLK
"uc_intrface_spissr<1>".AR "uc_intrface_spissr<2>".CLK
"uc_intrface_spissr<2>".AR "uc_intrface_spissr<3>".CLK
"uc_intrface_spissr<3>".AR "uc_intrface_spissr<4>".CLK
"uc_intrface_spissr<4>".AR "uc_intrface_spissr<5>".CLK
"uc_intrface_spissr<5>".AR "uc_intrface_spissr<6>".CLK
"uc_intrface_spissr<6>".AR "uc_intrface_spissr<7>".CLK
"uc_intrface_spissr<7>".AR "uc_intrface_spitr<0>".CLK
"uc_intrface_spitr<0>".AR "uc_intrface_spitr<1>".CLK "uc_intrface_spitr<1>".AR
"uc_intrface_spitr<2>".CLK "uc_intrface_spitr<2>".AR
"uc_intrface_spitr<3>".CLK "uc_intrface_spitr<3>".AR
"uc_intrface_spitr<4>".CLK "uc_intrface_spitr<4>".AR
"uc_intrface_spitr<5>".CLK "uc_intrface_spitr<5>".AR
"uc_intrface_spitr<6>".CLK "uc_intrface_spitr<6>".AR
"uc_intrface_spitr<7>".CLK "uc_intrface_spitr<7>".AR
"uc_intrface_xmit_empty_reset".CLK "uc_intrface_xmit_empty_reset".AR
"rcv_data<7>".D "rcv_data<7>".CLK "rcv_data<7>".AR "rcv_data<7>".CE
"spi_intrface_xmit_shift_reg_data_int<0>".CLK
"spi_intrface_xmit_shift_reg_data_int<0>".AR
"spi_intrface_xmit_shift_reg_data_int<1>".CLK
"spi_intrface_xmit_shift_reg_data_int<1>".AR
"spi_intrface_xmit_shift_reg_data_int<2>".CLK
"spi_intrface_xmit_shift_reg_data_int<2>".AR
"spi_intrface_xmit_shift_reg_data_int<3>".CLK
"spi_intrface_xmit_shift_reg_data_int<3>".AR
"spi_intrface_xmit_shift_reg_data_int<4>".CLK
"spi_intrface_xmit_shift_reg_data_int<4>".AR
"spi_intrface_xmit_shift_reg_data_int<5>".CLK
"spi_intrface_xmit_shift_reg_data_int<5>".AR
"spi_intrface_xmit_shift_reg_data_int<6>".CLK
"spi_intrface_xmit_shift_reg_data_int<6>".AR
"spi_intrface_xmit_shift_reg_data_int<7>".CLK
"spi_intrface_xmit_shift_reg_data_int<7>".AR "uc_intrface_spirr<0>".CLK
"uc_intrface_spirr<0>".AR "uc_intrface_spirr<1>".CLK "uc_intrface_spirr<1>".AR
"uc_intrface_spirr<2>".CLK "uc_intrface_spirr<2>".AR
"uc_intrface_spirr<3>".CLK "uc_intrface_spirr<3>".AR
"uc_intrface_spirr<4>".CLK "uc_intrface_spirr<4>".AR
"uc_intrface_spirr<5>".CLK "uc_intrface_spirr<5>".AR
"uc_intrface_spirr<6>".CLK "uc_intrface_spirr<6>".AR
"uc_intrface_spirr<7>".CLK "uc_intrface_spirr<7>".AR "xmit_empty".CLK
"xmit_empty".AR "uc_intrface_xmit_en".D "uc_intrface_xmit_en".CLK
"uc_intrface_xmit_en".AR "uc_intrface_rcv_en".D "uc_intrface_rcv_en".CLK
"uc_intrface_rcv_en".AR "uc_intrface_ssel_en".D "uc_intrface_ssel_en".CLK
"uc_intrface_ssel_en".AR "uc_intrface_stat_en".D "uc_intrface_stat_en".CLK
"uc_intrface_stat_en".AR "spi_intrface_spi_ctrl_sm_ss_in_int".D
"spi_intrface_spi_ctrl_sm_ss_in_int".CLK
"spi_intrface_spi_ctrl_sm_ss_in_int".AP "spi_intrface_SCK_GEN_sck_int".D
"spi_intrface_SCK_GEN_sck_int".CLK "spi_intrface_SCK_GEN_sck_int".AR
"spi_intrface_SCK_GEN_sck_d1".D "spi_intrface_SCK_GEN_sck_d1".CLK
"spi_intrface_SCK_GEN_sck_d1".AR "spi_intrface_SCK_GEN_sck_int_d1".D
"spi_intrface_SCK_GEN_sck_int_d1".CLK "spi_intrface_SCK_GEN_sck_int_d1".AR
"spi_intrface_rcv_shift_reg/rcv_bitcnt_int<0>".CLK
"spi_intrface_rcv_shift_reg/rcv_bitcnt_int<0>".AR
"uc_intrface_address_low<0>".D "uc_intrface_address_low<0>".CLK
"uc_intrface_address_low<0>".AR "uc_intrface_address_low<1>".D
"uc_intrface_address_low<1>".CLK "uc_intrface_address_low<1>".AR
"uc_intrface_address_low<2>".D "uc_intrface_address_low<2>".CLK
"uc_intrface_address_low<2>".AR "uc_intrface_address_low<3>".D
"uc_intrface_address_low<3>".CLK "uc_intrface_address_low<3>".AR
"uc_intrface_address_low<4>".D "uc_intrface_address_low<4>".CLK
"uc_intrface_address_low<4>".AR "uc_intrface_address_low<5>".D
"uc_intrface_address_low<5>".CLK "uc_intrface_address_low<5>".AR
"uc_intrface_address_low<6>".D "uc_intrface_address_low<6>".CLK
"uc_intrface_address_low<6>".AR "uc_intrface_address_low<7>".D
"uc_intrface_address_low<7>".CLK "uc_intrface_address_low<7>".AR
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