func_mux.vhd

VHDL写的LMS算法程序。利用本地正弦信号

-----------------------------------------------------------------------
-- File:  PCK_Func_MUX.vhd                              
-- Date:  Thu July 6 11:14:19 2005                                                      
--                                                                     
-- Copyright (C) 1999-2003 Easics NV.                 
-- This source file may be used and distributed without restriction    
-- provided that this copyright statement is not removed from the file 
-- and that any derivative work contains the original copyright notice
-- and the associated disclaimer.
--
-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
--
-- Purpose: -- A 8*8 fractional fixed-point value multiplier;
--
--                                                                     
-- Info: [e-mail]
--                                    
-----------------------------------------------------------------------


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

package PCK_multiplier is


  function multip							  
    ( A    :  std_logic_vector(7 DOWNTO 0);
      B    :  std_logic_vector(7 DOWNTO 0) )

  return std_logic_vector;

end PCK_multiplier;

-------------------------Function Declaration Ends--------------------------------------




LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;


package body PCK_multiplier is


  function multip							  
    ( A    :  std_logic_vector(7 DOWNTO 0);
      B    :  std_logic_vector(7 DOWNTO 0) )

      return std_logic_vector IS

 
     VARIABLE dataA                        :  std_logic_vector(7 DOWNTO 0);   
     VARIABLE dataB                        :  std_logic_vector(7 DOWNTO 0);   
 	VARIABLE dataOut                      :  std_logic_vector(13 DOWNTO 0);

     VARIABLE signFlag                     :	 std_logic;

    BEGIN
  
        dataA := A; 
	   dataB := B;

	   IF(A(7)='1') dataA:="11111111"- UNSIGNED(A)+1;		--Function:ABS();
	   IF(B(7)='1') dataB:="11111111"- UNSIGNED(B)+1;

	   signFlag := A(7) XOR B(7); 
	   dataOut := dataA(6 DOWNTO 0)*dataB(6 DOWNTO 0);

	   IF(signFlag = '1') dataOut(12 DOWNTO 5):="11111111" - dataOut(12 DOWNTO 5) +1;

    return dataOut(12 DOWNTO 5);


end PCK_multiplier;