costest.vhd

VHDL写的LMS算法程序。利用本地正弦信号

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-- You must compile the wrapper file costest.vhd when simulating
-- the core, costest. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY costest IS
	port (
	THETA: IN std_logic_VECTOR(5 downto 0);
	CLK: IN std_logic;
	ACLR: IN std_logic;
	ND: IN std_logic;
	RFD: OUT std_logic;
	RDY: OUT std_logic;
	SINE: OUT std_logic_VECTOR(7 downto 0));
END costest;

ARCHITECTURE costest_a OF costest IS

component wrapped_costest
	port (
	THETA: IN std_logic_VECTOR(5 downto 0);
	CLK: IN std_logic;
	ACLR: IN std_logic;
	ND: IN std_logic;
	RFD: OUT std_logic;
	RDY: OUT std_logic;
	SINE: OUT std_logic_VECTOR(7 downto 0));
end component;

-- Configuration specification 
	for all : wrapped_costest use entity XilinxCoreLib.C_SIN_COS_V4_2(behavioral)
		generic map(
			c_has_clk => 1,
			c_reg_input => 1,
			c_has_rdy => 1,
			c_has_sclr => 0,
			c_symmetric => 1,
			c_reg_output => 1,
			c_has_nd => 1,
			c_enable_rlocs => 0,
			c_has_rfd => 1,
			c_negative_sine => 0,
			c_latency => 3,
			c_pipe_stages => 1,
			c_has_ce => 0,
			c_has_aclr => 1,
			c_outputs_required => 0,
			c_theta_width => 6,
			c_mem_type => 1,
			c_negative_cosine => 0,
			c_output_width => 8);
BEGIN

U0 : wrapped_costest
		port map (
			THETA => THETA,
			CLK => CLK,
			ACLR => ACLR,
			ND => ND,
			RFD => RFD,
			RDY => RDY,
			SINE => SINE);
END costest_a;

-- synopsys translate_on