stack.v.bak

此代码可用modelsim进行仿真

/*****************************************/
/**        8bit RISC MCU desing         **/
/**           stack module              **/
/**            BY yuzhijie              **/
/**            2006.10.26               **/
/*****************************************/
`timescale 1ns/100ps
module stack(clk4,pc_addr,stack_call,stack_retlw,stack1);
    input clk4,stack_call,stack_retlw;
    input [10:0]pc_addr; 
    output [10:0]stack1;
    reg[10:0]stack1;
    reg[10:0]stack[1:0];      //stack[0]top of stack
always@(posedge clk4)
   begin
       if(stack_call==1) 
       begin
           stack[1]<=stack[0];
           stack[0]<=pc_addr+1;   //input stack CALL
       end
       else if(stack_retlw==1)
       begin
          stack1<=stack[0];
          stack[0]<=stack[1];   //output stack RETLW
       end
    end
endmodule