clk7.txt

ＦＰＧＡ数字钟的设计

library ieee;
use ieee.std_logic_1164.all;
entity clk7 is
  port (data: in std_logic_vector(3 downto 0);
      doute: out std_logic_vector(6 downto 0));
end entity clk7;
architecture behav of clk7 is
  begin

doute <= "1111110" when data="0000" else
         "0110000" when data="0001" else
         "1101101" when data="0010" else
         "1111001" when data="0011" else
         "0110011" when data="0100" else
         "1011011" when data="0101" else
         "1011111" when data="0110" else
         "1110000" when data="0111" else
         "1111111" when data="1000" else
         "1111011" when data="1001" else
         "XXXXXXX";
end architecture behav;