📄 m6_1scan.rpt
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LC | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC25 -> - - - - - - - * - - - - | - * | <-- |LPM_ADD_SUB:81|addcore:adder|addcore:adder0|result_node1
LC21 -> - - - - - - - - * - - - | - * | <-- |LPM_ADD_SUB:81|addcore:adder|addcore:adder0|result_node2
LC24 -> * * * * * * * * * * * * | - * | <-- sel0
LC23 -> * * * * * * - * * * * * | - * | <-- sel1
LC20 -> * * * * - * - * * * * * | - * | <-- sel2
LC18 -> - - * - - - - - - - - - | - * | <-- ~318~1
LC17 -> - * - - - - - - - - - - | - * | <-- ~336~1
LC27 -> * - - - - - - - - - - - | - * | <-- ~354~1
Pin
43 -> - - - - - - - - - - - - | - - | <-- clkscan
37 -> * - - - - - - - - - - * | - * | <-- in10
36 -> - * - - - - - - - - * - | - * | <-- in11
32 -> - - * - - - - - - * - - | - * | <-- in12
29 -> - - - * - - - - - - - - | - * | <-- in13
27 -> * - - - - - - - - - - * | - * | <-- in20
25 -> - * - - - - - - - - * - | - * | <-- in21
39 -> - - * - - - - - - * - - | - * | <-- in22
40 -> - - - * - - - - - - - - | - * | <-- in23
41 -> * - - - - - - - - - - * | - * | <-- in30
21 -> - * - - - - - - - - * - | - * | <-- in31
4 -> - - * - - - - - - * - - | - * | <-- in32
5 -> - - - * - - - - - - - - | - * | <-- in33
6 -> * - - - - - - - - - - - | - * | <-- in40
7 -> - * - - - - - - - - - - | - * | <-- in41
8 -> - - * - - - - - - - - - | - * | <-- in42
9 -> - - - * - - - - - - - - | - * | <-- in43
11 -> * - - - - - - - - - - * | - * | <-- in50
12 -> - * - - - - - - - - * - | - * | <-- in51
13 -> - - * - - - - - - * - - | - * | <-- in52
14 -> - - - * - - - - - - - - | - * | <-- in53
16 -> * - - - - - - - - - - * | - * | <-- in60
17 -> - * - - - - - - - - * - | - * | <-- in61
18 -> - - * - - - - - - * - - | - * | <-- in62
19 -> - - - * - - - - - - - - | - * | <-- in63
20 -> - - - - - - * * * - - - | - * | <-- reset
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\wy\m6_1scan.rpt
m6_1scan
** EQUATIONS **
clkscan : INPUT;
in10 : INPUT;
in11 : INPUT;
in12 : INPUT;
in13 : INPUT;
in20 : INPUT;
in21 : INPUT;
in22 : INPUT;
in23 : INPUT;
in30 : INPUT;
in31 : INPUT;
in32 : INPUT;
in33 : INPUT;
in40 : INPUT;
in41 : INPUT;
in42 : INPUT;
in43 : INPUT;
in50 : INPUT;
in51 : INPUT;
in52 : INPUT;
in53 : INPUT;
in60 : INPUT;
in61 : INPUT;
in62 : INPUT;
in63 : INPUT;
reset : INPUT;
-- Node name is 'data0'
-- Equation name is 'data0', location is LC026, type is output.
data0 = LCELL( _EQ001 $ _EQ002);
_EQ001 = !in10 & !in20 & !in30 & !in40 & !_LC027 & !sel2 & _X001
# !in10 & !in20 & !in50 & !in60 & !_LC027 & !sel1 & _X001
# !in10 & !in30 & !in50 & !in60 & !_LC027 & !sel0 & _X001
# !in40 & !_LC027 & sel0 & sel1 & !sel2 & _X001;
_X001 = EXP(!in60 & sel0 & sel2);
_EQ002 = !_LC027 & _X001;
_X001 = EXP(!in60 & sel0 & sel2);
-- Node name is 'data1'
-- Equation name is 'data1', location is LC028, type is output.
data1 = LCELL( _EQ003 $ _EQ004);
_EQ003 = !in11 & !in21 & !in31 & !in41 & !_LC017 & !sel2 & _X002
# !in11 & !in21 & !in51 & !in61 & !_LC017 & !sel1 & _X002
# !in11 & !in31 & !in51 & !in61 & !_LC017 & !sel0 & _X002
# !in41 & !_LC017 & sel0 & sel1 & !sel2 & _X002;
_X002 = EXP(!in61 & sel0 & sel2);
_EQ004 = !_LC017 & _X002;
_X002 = EXP(!in61 & sel0 & sel2);
-- Node name is 'data2'
-- Equation name is 'data2', location is LC032, type is output.
data2 = LCELL( _EQ005 $ _EQ006);
_EQ005 = !in12 & !in22 & !in32 & !in42 & !_LC018 & !sel2 & _X003
# !in12 & !in22 & !in52 & !in62 & !_LC018 & !sel1 & _X003
# !in12 & !in32 & !in52 & !in62 & !_LC018 & !sel0 & _X003
# !in42 & !_LC018 & sel0 & sel1 & !sel2 & _X003;
_X003 = EXP(!in62 & sel0 & sel2);
_EQ006 = !_LC018 & _X003;
_X003 = EXP(!in62 & sel0 & sel2);
-- Node name is 'data3'
-- Equation name is 'data3', location is LC030, type is output.
data3 = LCELL( _EQ007 $ _EQ008);
_EQ007 = !in13 & !in23 & !in33 & !in43 & !sel2 & _X004 & _X005 & _X006 &
_X007 & _X008 & _X009
# !in13 & !in23 & !in53 & !in63 & !sel1 & _X004 & _X005 & _X006 &
_X007 & _X008 & _X009
# !in13 & !in33 & !in53 & !in63 & !sel0 & _X004 & _X005 & _X006 &
_X007 & _X008 & _X009
# !in43 & sel0 & sel1 & !sel2 & _X004 & _X005 & _X006 & _X007 &
_X008 & _X009;
_X004 = EXP(!in23 & sel0 & !sel1 & !sel2);
_X005 = EXP(!in63 & sel0 & sel2);
_X006 = EXP(!in33 & !sel0 & sel1 & !sel2);
_X007 = EXP(!in53 & !sel0 & !sel1 & sel2);
_X008 = EXP(!in13 & !sel0 & !sel1 & !sel2);
_X009 = EXP(!in63 & sel1 & sel2);
_EQ008 = _X004 & _X005 & _X006 & _X007 & _X008 & _X009;
_X004 = EXP(!in23 & sel0 & !sel1 & !sel2);
_X005 = EXP(!in63 & sel0 & sel2);
_X006 = EXP(!in33 & !sel0 & sel1 & !sel2);
_X007 = EXP(!in53 & !sel0 & !sel1 & sel2);
_X008 = EXP(!in13 & !sel0 & !sel1 & !sel2);
_X009 = EXP(!in63 & sel1 & sel2);
-- Node name is 'sel0' = 'count0'
-- Equation name is 'sel0', location is LC024, type is output.
sel0 = TFFE( VCC, GLOBAL( clkscan), !reset, VCC, VCC);
-- Node name is 'sel1' = 'count1'
-- Equation name is 'sel1', location is LC023, type is output.
sel1 = DFFE( _EQ009 $ _LC025, GLOBAL( clkscan), !reset, VCC, VCC);
_EQ009 = _LC025 & sel0 & !sel1 & sel2;
-- Node name is 'sel2' = 'count2'
-- Equation name is 'sel2', location is LC020, type is output.
sel2 = DFFE( _EQ010 $ _LC021, GLOBAL( clkscan), !reset, VCC, VCC);
_EQ010 = _LC021 & sel0 & !sel1 & sel2;
-- Node name is '|LPM_ADD_SUB:81|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried
_LC025 = LCELL( sel1 $ sel0);
-- Node name is '|LPM_ADD_SUB:81|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC021', type is buried
_LC021 = LCELL( sel2 $ _EQ011);
_EQ011 = sel0 & sel1;
-- Node name is '~318~1'
-- Equation name is '~318~1', location is LC018, type is buried.
-- synthesized logic cell
_LC018 = LCELL( _EQ012 $ GND);
_EQ012 = !in22 & sel0 & !sel1 & !sel2
# !in32 & !sel0 & sel1 & !sel2
# !in52 & !sel0 & !sel1 & sel2
# !in12 & !sel0 & !sel1 & !sel2
# !in62 & sel1 & sel2;
-- Node name is '~336~1'
-- Equation name is '~336~1', location is LC017, type is buried.
-- synthesized logic cell
_LC017 = LCELL( _EQ013 $ GND);
_EQ013 = !in21 & sel0 & !sel1 & !sel2
# !in31 & !sel0 & sel1 & !sel2
# !in51 & !sel0 & !sel1 & sel2
# !in11 & !sel0 & !sel1 & !sel2
# !in61 & sel1 & sel2;
-- Node name is '~354~1'
-- Equation name is '~354~1', location is LC027, type is buried.
-- synthesized logic cell
_LC027 = LCELL( _EQ014 $ GND);
_EQ014 = !in20 & sel0 & !sel1 & !sel2
# !in30 & !sel0 & sel1 & !sel2
# !in50 & !sel0 & !sel1 & sel2
# !in10 & !sel0 & !sel1 & !sel2
# !in60 & sel1 & sel2;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\wy\m6_1scan.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 8,216K
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