📄 m6_1scan.rpt
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Project Information e:\wy\m6_1scan.rpt
MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 10/31/2006 17:04:25
Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
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their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
M6_1SCAN
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
m6_1scan EPM7032LC44-6 26 7 0 12 9 37 %
User Pins: 26 7 0
Project Information e:\wy\m6_1scan.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clkscan' chosen for auto global Clock
Project Information e:\wy\m6_1scan.rpt
** FILE HIERARCHY **
|lpm_add_sub:81|
|lpm_add_sub:81|addcore:adder|
|lpm_add_sub:81|addcore:adder|addcore:adder0|
|lpm_add_sub:81|altshift:result_ext_latency_ffs|
|lpm_add_sub:81|altshift:carry_ext_latency_ffs|
|lpm_add_sub:81|altshift:oflow_ext_latency_ffs|
Device-Specific Information: e:\wy\m6_1scan.rpt
m6_1scan
***** Logic for device 'm6_1scan' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
Device-Specific Information: e:\wy\m6_1scan.rpt
m6_1scan
** ERROR SUMMARY **
Info: Chip 'm6_1scan' in device 'EPM7032LC44-6' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger device
c
l
k
i i i s i i
n n n V G G G c G n n
4 3 3 C N N N a N 3 2
0 3 2 C D D D n D 0 3
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
in41 | 7 39 | in22
in42 | 8 38 | sel2
in43 | 9 37 | in10
GND | 10 36 | in11
in50 | 11 35 | VCC
in51 | 12 EPM7032LC44-6 34 | sel1
in52 | 13 33 | sel0
in53 | 14 32 | in12
VCC | 15 31 | data0
in60 | 16 30 | GND
in61 | 17 29 | in13
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
i i r i G V d i d i d
n n e n N C a n a n a
6 6 s 3 D C t 2 t 2 t
2 3 e 1 a 1 a 0 a
t 2 3 1
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\wy\m6_1scan.rpt
m6_1scan
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 16/16(100%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 12/16( 75%) 16/16(100%) 16/16(100%) 33/36( 91%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 32/32 (100%)
Total logic cells used: 12/32 ( 37%)
Total shareable expanders used: 9/32 ( 28%)
Total Turbo logic cells used: 12/32 ( 37%)
Total shareable expanders not available (n/a): 7/32 ( 21%)
Average fan-in: 6.91
Total fan-in: 83
Total input pins required: 26
Total output pins required: 7
Total bidirectional pins required: 0
Total logic cells required: 12
Total flipflops required: 3
Total product terms required: 56
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 9
Synthesized logic cells: 3/ 32 ( 9%)
Device-Specific Information: e:\wy\m6_1scan.rpt
m6_1scan
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
43 - - INPUT G 0 0 0 0 0 0 0 clkscan
37 (21) (B) INPUT 0 0 0 0 0 1 1 in10
36 (22) (B) INPUT 0 0 0 0 0 1 1 in11
32 (25) (B) INPUT 0 0 0 0 0 1 1 in12
29 (27) (B) INPUT 0 0 0 0 0 1 0 in13
27 (29) (B) INPUT 0 0 0 0 0 1 1 in20
25 (31) (B) INPUT 0 0 0 0 0 1 1 in21
39 (19) (B) INPUT 0 0 0 0 0 1 1 in22
40 (18) (B) INPUT 0 0 0 0 0 1 0 in23
41 (17) (B) INPUT 0 0 0 0 0 1 1 in30
21 (16) (A) INPUT 0 0 0 0 0 1 1 in31
4 (1) (A) INPUT 0 0 0 0 0 1 1 in32
5 (2) (A) INPUT 0 0 0 0 0 1 0 in33
6 (3) (A) INPUT 0 0 0 0 0 1 0 in40
7 (4) (A) INPUT 0 0 0 0 0 1 0 in41
8 (5) (A) INPUT 0 0 0 0 0 1 0 in42
9 (6) (A) INPUT 0 0 0 0 0 1 0 in43
11 (7) (A) INPUT 0 0 0 0 0 1 1 in50
12 (8) (A) INPUT 0 0 0 0 0 1 1 in51
13 (9) (A) INPUT 0 0 0 0 0 1 1 in52
14 (10) (A) INPUT 0 0 0 0 0 1 0 in53
16 (11) (A) INPUT 0 0 0 0 0 1 1 in60
17 (12) (A) INPUT 0 0 0 0 0 1 1 in61
18 (13) (A) INPUT 0 0 0 0 0 1 1 in62
19 (14) (A) INPUT 0 0 0 0 0 1 0 in63
20 (15) (A) INPUT 0 0 0 0 0 3 0 reset
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\wy\m6_1scan.rpt
m6_1scan
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
31 26 B OUTPUT t 2 0 1 6 4 0 0 data0
28 28 B OUTPUT t 2 0 1 6 4 0 0 data1
24 32 B OUTPUT t 2 0 1 6 4 0 0 data2
26 30 B OUTPUT t 7 0 1 6 3 0 0 data3
33 24 B FF + t 0 0 0 1 0 6 5 sel0 (:36)
34 23 B FF + t 0 0 0 1 4 6 5 sel1 (:35)
38 20 B FF + t 0 0 0 1 4 6 4 sel2 (:34)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\wy\m6_1scan.rpt
m6_1scan
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(32) 25 B SOFT t 0 0 0 0 2 1 0 |LPM_ADD_SUB:81|addcore:adder|addcore:adder0|result_node1
(37) 21 B SOFT t 0 0 0 0 3 1 0 |LPM_ADD_SUB:81|addcore:adder|addcore:adder0|result_node2
(40) 18 B SOFT s t 1 0 1 5 3 1 0 ~318~1
(41) 17 B SOFT s t 1 0 1 5 3 1 0 ~336~1
(29) 27 B SOFT s t 1 0 1 5 3 1 0 ~354~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\wy\m6_1scan.rpt
m6_1scan
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+----------------------- LC26 data0
| +--------------------- LC28 data1
| | +------------------- LC32 data2
| | | +----------------- LC30 data3
| | | | +--------------- LC25 |LPM_ADD_SUB:81|addcore:adder|addcore:adder0|result_node1
| | | | | +------------- LC21 |LPM_ADD_SUB:81|addcore:adder|addcore:adder0|result_node2
| | | | | | +----------- LC24 sel0
| | | | | | | +--------- LC23 sel1
| | | | | | | | +------- LC20 sel2
| | | | | | | | | +----- LC18 ~318~1
| | | | | | | | | | +--- LC17 ~336~1
| | | | | | | | | | | +- LC27 ~354~1
| | | | | | | | | | | |
| | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | that feed LAB 'B'
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