📄 clock.rpt
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| | | | | +--------------------- LC81 |CLK7:12|~332~7
| | | | | | +------------------- LC82 |CLK7:12|~332~8
| | | | | | | +----------------- LC89 |CLK7:12|~404~2
| | | | | | | | +--------------- LC85 |CLK7:12|~470~1
| | | | | | | | | +------------- LC90 |CLK7:12|~503~3
| | | | | | | | | | +----------- LC91 |CLK7:12|~569~2
| | | | | | | | | | | +--------- LC86 |NEWHOUR:11|LPM_ADD_SUB:227|addcore:adder|addcore:adder0|result_node1
| | | | | | | | | | | | +------- LC84 |NEWHOUR:11|hourt13
| | | | | | | | | | | | | +----- LC94 |NEWMINUTE:4|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node3
| | | | | | | | | | | | | | +--- LC83 |NEWSECOND:5|sect13
| | | | | | | | | | | | | | | +- LC93 |NEWSECOND:5|sect11
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'F'
LC | | | | | | | | | | | | | | | | | A B C D E F | Logic cells that feed LAB 'F':
LC84 -> * - - - * - - * * - * - * - - - | * - * * * * | <-- |NEWHOUR:11|hourt13
LC83 -> - - - - - - - - - * - - - - * * | - - - * * * | <-- |NEWSECOND:5|sect13
LC93 -> - - - - - - - - - - - - - - * * | - - * * * * | <-- |NEWSECOND:5|sect11
Pin
67 -> - - - - - - - - - - - - - - - - | - - - - - - | <-- clk
13 -> - - - - - - - - - - - - * - * * | - * * - * * | <-- reset
LC41 -> - - - - - - - * - * - - - - - - | * * - * * * | <-- |CLK7:12|~332~1
LC6 -> - - - - - - - * - * - - - - - - | * * - * * * | <-- |CLK7:12|~344~1
LC13 -> - - - - - - - * * - * - - - - - | * * - * * * | <-- |CLK7:12|~356~1
LC43 -> - - - - - - - - - - - - * - - - | - - - - - * | <-- |NEWHOUR:11|LPM_ADD_SUB:227|addcore:adder|addcore:adder0|result_node3
LC37 -> * - - * - - - * * - * - * - - - | * - * * * * | <-- |NEWHOUR:11|hourt12
LC44 -> * - - - - - - - * - * * * - - - | - - * * * * | <-- |NEWHOUR:11|hourt11
LC42 -> * - - - - * - - * - - * * - - - | - - * * * * | <-- |NEWHOUR:11|hourt10
LC35 -> - * - - - - - * - * - - * - - - | * * * * * * | <-- |NEWHOUR:11|hourt23
LC34 -> - - - - - - - * - * - - * - - - | * * * * * * | <-- |NEWHOUR:11|hourt22
LC33 -> - - - * - - * * - - - - * - - - | * * * * * * | <-- |NEWHOUR:11|hourt21
LC36 -> - * * - - * - - - - - - * - - - | * * * * * * | <-- |NEWHOUR:11|hourt20
LC29 -> - - - - - - - - - - - - * - - - | - * * - - * | <-- |NEWMINUTE:4|:11
LC18 -> * - - - * - - * * - * - - * - - | * * - * * * | <-- |NEWMINUTE:4|mint13
LC20 -> * - - * - - - * * - * - - * - - | * * - * * * | <-- |NEWMINUTE:4|mint12
LC25 -> * - - - - * * - * - * - - * - - | - * * * * * | <-- |NEWMINUTE:4|mint11
LC26 -> * - - - * * - - * - - - - * - - | - * * * * * | <-- |NEWMINUTE:4|mint10
LC28 -> * * * - - - - * * - * - - - - - | * * - * - * | <-- |NEWMINUTE:4|mint23
LC27 -> * * * - - - - * * - * - - - - - | * * * * - * | <-- |NEWMINUTE:4|mint22
LC22 -> * - * * - * * - * - * - - - - - | - * - * - * | <-- |NEWMINUTE:4|mint21
LC23 -> * - * - * * - - * - * - - - - - | - * - * - * | <-- |NEWMINUTE:4|mint20
LC78 -> - - - - - - - - - - - - - - - * | - - - - - * | <-- |NEWSECOND:5|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node1
LC68 -> - - - - - - - - - - - - - - * - | - - - - - * | <-- |NEWSECOND:5|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node3
LC38 -> - - - - - - - - - * - - - - * * | - - - * * * | <-- |NEWSECOND:5|sect12
LC31 -> - - - - - - - - - - - - - - * * | - - * * * * | <-- |NEWSECOND:5|sect10
LC73 -> * * - * - - - - * * * - - - - - | * - * * * * | <-- |NEWSECOND:5|sect23
LC75 -> * * - * - - - - * * * - - - - - | * - * * * * | <-- |NEWSECOND:5|sect22
LC65 -> * - - - - - * - * - * - - - - - | - - - * * * | <-- |NEWSECOND:5|sect21
LC74 -> * - - - * * - - * - - - - - - - | - - - * * * | <-- |NEWSECOND:5|sect20
LC32 -> * * * * * * * * * * * - - - - - | * * * * * * | <-- sel0
LC19 -> * - * * * * * * * * * - - - - - | * * * * * * | <-- sel1
LC17 -> * - * * * * * * * * * - - - - - | * * * * * * | <-- sel2
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\wy\clock.rpt
clock
** EQUATIONS **
clk : INPUT;
clkscan : INPUT;
reset : INPUT;
-- Node name is 'sel0' = '|M6_1SCAN:2|count0'
-- Equation name is 'sel0', type is output
sel0 = TFFE( VCC, clkscan, !reset, VCC, VCC);
-- Node name is 'sel1' = '|M6_1SCAN:2|count1'
-- Equation name is 'sel1', type is output
sel1 = DFFE( _EQ001 $ _LC066, clkscan, !reset, VCC, VCC);
_EQ001 = _LC066 & sel0 & !sel1 & sel2;
-- Node name is 'sel2' = '|M6_1SCAN:2|count2'
-- Equation name is 'sel2', type is output
sel2 = DFFE( _EQ002 $ _LC008, clkscan, !reset, VCC, VCC);
_EQ002 = _LC008 & sel0 & !sel1 & sel2;
-- Node name is '7seg0'
-- Equation name is '7seg0', location is LC024, type is output.
7seg0 = LCELL( _EQ003 $ VCC);
_EQ003 = !_LC049 & !_LC050 & !_LC056 & !_LC079 & !_LC091 & _X001 & _X002 &
_X003 & _X004 & _X005 & _X006 & _X007 & _X008 & _X009 &
_X010;
_X001 = EXP(!_LC013 & _LC033 & _LC034 & !_LC035 & sel0 & sel2);
_X002 = EXP(!_LC013 & !_LC033 & !_LC034 & _LC035 & sel0 & sel2);
_X003 = EXP(!_LC033 & !_LC034 & !_LC035 & !_LC036 & sel1 & sel2);
_X004 = EXP(!_LC013 & _LC033 & _LC034 & !_LC035 & sel1 & sel2);
_X005 = EXP(!_LC013 & _LC034 & !_LC035 & _LC036 & sel1 & sel2);
_X006 = EXP(!_LC013 & _LC034 & !_LC035 & _LC036 & sel0 & sel2);
_X007 = EXP(!_LC033 & !_LC034 & !_LC035 & !_LC036 & sel0 & sel2);
_X008 = EXP( _LC006 & !_LC013);
_X009 = EXP(!_LC013 & _LC041);
_X010 = EXP(!_LC013 & !_LC033 & !_LC034 & _LC035 & sel1 & sel2);
-- Node name is '7seg1'
-- Equation name is '7seg1', location is LC014, type is output.
7seg1 = LCELL( _EQ004 $ VCC);
_EQ004 = !_LC041 & !_LC049 & !_LC050 & !_LC051 & !_LC054 & !_LC055 &
!_LC058 & !_LC060 & !_LC061 & !_LC064 & _X003 & _X007 & _X011 &
_X012 & _X013 & _X014 & _X015 & _X016 & _X017 & _X018 &
_X019 & _X020;
_X003 = EXP(!_LC033 & !_LC034 & !_LC035 & !_LC036 & sel1 & sel2);
_X007 = EXP(!_LC033 & !_LC034 & !_LC035 & !_LC036 & sel0 & sel2);
_X011 = EXP(!_LC033 & _LC034 & !_LC035 & !_LC036 & sel1 & sel2);
_X012 = EXP( _LC033 & _LC034 & !_LC035 & _LC036 & sel1 & sel2);
_X013 = EXP( _LC033 & _LC034 & !_LC035 & _LC036 & sel0 & sel2);
_X014 = EXP(!_LC033 & _LC034 & !_LC035 & !_LC036 & sel0 & sel2);
_X015 = EXP(!_LC033 & !_LC034 & _LC035 & sel0 & sel2);
_X016 = EXP(!_LC033 & !_LC034 & _LC035 & sel1 & sel2);
_X017 = EXP(!_LC033 & !_LC034 & !_LC035 & _LC036 & sel0 & sel2);
_X018 = EXP(!_LC033 & !_LC034 & !_LC035 & _LC036 & sel1 & sel2);
_X019 = EXP( _LC033 & !_LC034 & !_LC035 & !_LC036 & sel1 & sel2);
_X020 = EXP( _LC033 & !_LC034 & !_LC035 & !_LC036 & sel0 & sel2);
-- Node name is '7seg2'
-- Equation name is '7seg2', location is LC012, type is output.
7seg2 = LCELL( _EQ005 $ VCC);
_EQ005 = !_LC005 & !_LC013 & !_LC057 & !_LC076 & !_LC090;
-- Node name is '7seg3'
-- Equation name is '7seg3', location is LC021, type is output.
7seg3 = LCELL( _EQ006 $ VCC);
_EQ006 = !_LC049 & !_LC050 & !_LC056 & !_LC063 & !_LC085 & _X002 & _X003 &
_X007 & _X008 & _X009 & _X010 & _X021 & _X022 & _X023 &
_X024;
_X002 = EXP(!_LC013 & !_LC033 & !_LC034 & _LC035 & sel0 & sel2);
_X003 = EXP(!_LC033 & !_LC034 & !_LC035 & !_LC036 & sel1 & sel2);
_X007 = EXP(!_LC033 & !_LC034 & !_LC035 & !_LC036 & sel0 & sel2);
_X008 = EXP( _LC006 & !_LC013);
_X009 = EXP(!_LC013 & _LC041);
_X010 = EXP(!_LC013 & !_LC033 & !_LC034 & _LC035 & sel1 & sel2);
_X021 = EXP(!_LC013 & _LC033 & _LC034 & !_LC035 & !_LC036 & sel1 & sel2);
_X022 = EXP(!_LC013 & _LC033 & _LC034 & !_LC035 & !_LC036 & sel0 & sel2);
_X023 = EXP(!_LC013 & !_LC033 & _LC034 & !_LC035 & _LC036 & sel1 & sel2);
_X024 = EXP(!_LC013 & !_LC033 & _LC034 & !_LC035 & _LC036 & sel0 & sel2);
-- Node name is '7seg4'
-- Equation name is '7seg4', location is LC072, type is output.
7seg4 = LCELL( _EQ007 $ VCC);
_EQ007 = !_LC049 & !_LC050 & !_LC053 & !_LC062 & _X003 & _X007 & _X008 &
_X025 & _X026 & _X027 & _X028;
_X003 = EXP(!_LC033 & !_LC034 & !_LC035 & !_LC036 & sel1 & sel2);
_X007 = EXP(!_LC033 & !_LC034 & !_LC035 & !_LC036 & sel0 & sel2);
_X008 = EXP( _LC006 & !_LC013);
_X025 = EXP(!_LC013 & !_LC033 & !_LC034 & _LC035 & !_LC036 & !_LC041 & sel1 &
sel2);
_X026 = EXP(!_LC013 & !_LC033 & !_LC034 & _LC035 & !_LC036 & !_LC041 & sel0 &
sel2);
_X027 = EXP(!_LC013 & _LC033 & _LC034 & !_LC035 & !_LC036 & !_LC041 & sel1 &
sel2);
_X028 = EXP(!_LC013 & _LC033 & _LC034 & !_LC035 & !_LC036 & !_LC041 & sel0 &
sel2);
-- Node name is '7seg5'
-- Equation name is '7seg5', location is LC069, type is output.
7seg5 = LCELL( _EQ008 $ VCC);
_EQ008 = !_LC052 & !_LC076 & !_LC089 & _X029 & _X030 & _X031 & _X032;
_X029 = EXP(!_LC006 & !_LC013 & !_LC041 & !_LC073 & _LC075 & sel0 & !sel1 &
!sel2);
_X030 = EXP(!_LC006 & !_LC013 & _LC038 & !_LC041 & !_LC083 & !sel0 & !sel1 &
!sel2);
_X031 = EXP(!_LC006 & !_LC013 & _LC034 & !_LC035 & !_LC041 & sel1 & sel2);
_X032 = EXP(!_LC006 & !_LC013 & _LC034 & !_LC035 & !_LC041 & sel0 & sel2);
-- Node name is '7seg6'
-- Equation name is '7seg6', location is LC009, type is output.
7seg6 = LCELL( _EQ009 $ GND);
_EQ009 = !_LC013 & !_LC076 & _X033;
_X033 = EXP(!_LC006 & !_LC011 & !_LC041 & !_LC045);
-- Node name is '|CLK7:12|~324~1'
-- Equation name is '_LC011', type is buried
-- synthesized logic cell
_LC011 = LCELL( _EQ010 $ VCC);
_EQ010 = !_LC059 & !_LC064 & _X011 & _X014;
_X011 = EXP(!_LC033 & _LC034 & !_LC035 & !_LC036 & sel1 & sel2);
_X014 = EXP(!_LC033 & _LC034 & !_LC035 & !_LC036 & sel0 & sel2);
-- Node name is '|CLK7:12|~324~2'
-- Equation name is '_LC064', type is buried
-- synthesized logic cell
_LC064 = LCELL( _EQ011 $ GND);
_EQ011 = !_LC022 & !_LC023 & _LC027 & !_LC028 & sel0 & sel1 & !sel2
# !_LC065 & !_LC073 & !_LC074 & _LC075 & sel0 & !sel1 & !sel2
# !_LC018 & _LC020 & !_LC025 & !_LC026 & !sel0 & sel1 & !sel2
# _LC037 & !_LC042 & !_LC044 & !_LC084 & !sel0 & !sel1 & sel2
# !_LC031 & _LC038 & !_LC083 & !_LC093 & !sel0 & !sel1 & !sel2;
-- Node name is '|CLK7:12|~324~3'
-- Equation name is '_LC059', type is buried
-- synthesized logic cell
_LC059 = LCELL( _EQ012 $ GND);
_EQ012 = !_LC018 & _LC020 & !_LC022 & !_LC023 & !_LC025 & !_LC026 &
_LC027 & !_LC028 & !_LC031 & _LC038 & !_LC065 & !_LC073 &
!_LC074 & _LC075 & !_LC083 & !_LC093 & !sel2
# !_LC018 & _LC020 & !_LC025 & !_LC026 & !_LC031 & !_LC033 &
_LC034 & !_LC035 & !_LC036 & _LC037 & _LC038 & !_LC042 &
!_LC044 & !_LC083 & !_LC084 & !_LC093 & !sel0
# !_LC031 & !_LC033 & _LC034 & !_LC035 & !_LC036 & _LC037 &
_LC038 & !_LC042 & !_LC044 & !_LC065 & !_LC073 & !_LC074 &
_LC075 & !_LC083 & !_LC084 & !_LC093 & !sel1
# !_LC018 & _LC020 & !_LC022 & !_LC023 & !_LC025 & !_LC026 &
_LC027 & !_LC028 & !_LC033 & _LC034 & !_LC035 & !_LC036 &
sel1
# !_LC022 & !_LC023 & _LC027 & !_LC028 & !_LC033 & _LC034 &
!_LC035 & !_LC036 & !_LC065 & !_LC073 & !_LC074 & _LC075 &
sel0;
-- Node name is '|CLK7:12|~325~1'
-- Equation name is '_LC045', type is buried
-- synthesized logic cell
_LC045 = LCELL( _EQ013 $ VCC);
_EQ013 = !_LC054 & !_LC077 & !_LC095 & _X015 & _X016 & _X034 & _X035 &
_X036 & _X037;
_X015 = EXP(!_LC033 & !_LC034 & _LC035 & sel0 & sel2);
_X016 = EXP(!_LC033 & !_LC034 & _LC035 & sel1 & sel2);
_X034 = EXP(!_LC033 & _LC034 & !_LC035 & _LC036 & sel0 & sel2);
_X035 = EXP(!_LC033 & _LC034 & !_LC035 & _LC036 & sel1 & sel2);
_X036 = EXP( _LC033 & _LC034 & !_LC035 & !_LC036 & sel0 & sel2);
_X037 = EXP( _LC033 & _LC034 & !_LC035 & !_LC036 & sel1 & sel2);
-- Node name is '|CLK7:12|~325~2'
-- Equation name is '_LC054', type is buried
-- synthesized logic cell
_LC054 = LCELL( _EQ014 $ GND);
_EQ014 = !_LC022 & !_LC027 & _LC028 & sel0 & sel1 & !sel2
# !_LC065 & _LC073 & !_LC075 & sel0 & !sel1 & !sel2
# _LC018 & !_LC020 & !_LC025 & !sel0 & sel1 & !sel2
# !_LC037 & !_LC044 & _LC084 & !sel0 & !sel1 & sel2
# !_LC038 & _LC083 & !_LC093 & !sel0 & !sel1 & !sel2;
-- Node name is '|CLK7:12|~325~3'
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