clock.rpt

ＦＰＧＡ数字钟的设计

Project Information                                            e:\wy\clock.rpt

MAX+plus II Compiler Report File
Version 10.0 9/14/2000
Compiled: 10/31/2006 17:16:29

Copyright (C) 1988-2000 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful




** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

clock     EPM7096LC68-7    3        10       0      85      49          88 %

User Pins:                 3        10       0  



Project Information                                            e:\wy\clock.rpt

** AUTO GLOBAL SIGNALS **



INFO: Signal 'clk' chosen for auto global Clock


Project Information                                            e:\wy\clock.rpt

** FILE HIERARCHY **



|m6_1scan:2|
|m6_1scan:2|lpm_add_sub:81|
|m6_1scan:2|lpm_add_sub:81|addcore:adder|
|m6_1scan:2|lpm_add_sub:81|addcore:adder|addcore:adder0|
|m6_1scan:2|lpm_add_sub:81|altshift:result_ext_latency_ffs|
|m6_1scan:2|lpm_add_sub:81|altshift:carry_ext_latency_ffs|
|m6_1scan:2|lpm_add_sub:81|altshift:oflow_ext_latency_ffs|
|newminute:4|
|newminute:4|lpm_add_sub:129|
|newminute:4|lpm_add_sub:129|addcore:adder|
|newminute:4|lpm_add_sub:129|addcore:adder|addcore:adder0|
|newminute:4|lpm_add_sub:129|altshift:result_ext_latency_ffs|
|newminute:4|lpm_add_sub:129|altshift:carry_ext_latency_ffs|
|newminute:4|lpm_add_sub:129|altshift:oflow_ext_latency_ffs|
|newminute:4|lpm_add_sub:188|
|newminute:4|lpm_add_sub:188|addcore:adder|
|newminute:4|lpm_add_sub:188|addcore:adder|addcore:adder0|
|newminute:4|lpm_add_sub:188|altshift:result_ext_latency_ffs|
|newminute:4|lpm_add_sub:188|altshift:carry_ext_latency_ffs|
|newminute:4|lpm_add_sub:188|altshift:oflow_ext_latency_ffs|
|newsecond:5|
|newsecond:5|lpm_add_sub:129|
|newsecond:5|lpm_add_sub:129|addcore:adder|
|newsecond:5|lpm_add_sub:129|addcore:adder|addcore:adder0|
|newsecond:5|lpm_add_sub:129|altshift:result_ext_latency_ffs|
|newsecond:5|lpm_add_sub:129|altshift:carry_ext_latency_ffs|
|newsecond:5|lpm_add_sub:129|altshift:oflow_ext_latency_ffs|
|newsecond:5|lpm_add_sub:188|
|newsecond:5|lpm_add_sub:188|addcore:adder|
|newsecond:5|lpm_add_sub:188|addcore:adder|addcore:adder0|
|newsecond:5|lpm_add_sub:188|altshift:result_ext_latency_ffs|
|newsecond:5|lpm_add_sub:188|altshift:carry_ext_latency_ffs|
|newsecond:5|lpm_add_sub:188|altshift:oflow_ext_latency_ffs|
|newhour:11|
|newhour:11|lpm_add_sub:168|
|newhour:11|lpm_add_sub:168|addcore:adder|
|newhour:11|lpm_add_sub:168|addcore:adder|addcore:adder0|
|newhour:11|lpm_add_sub:168|altshift:result_ext_latency_ffs|
|newhour:11|lpm_add_sub:168|altshift:carry_ext_latency_ffs|
|newhour:11|lpm_add_sub:168|altshift:oflow_ext_latency_ffs|
|newhour:11|lpm_add_sub:227|
|newhour:11|lpm_add_sub:227|addcore:adder|
|newhour:11|lpm_add_sub:227|addcore:adder|addcore:adder0|
|newhour:11|lpm_add_sub:227|altshift:result_ext_latency_ffs|
|newhour:11|lpm_add_sub:227|altshift:carry_ext_latency_ffs|
|newhour:11|lpm_add_sub:227|altshift:oflow_ext_latency_ffs|
|clk7:12|


Device-Specific Information:                                   e:\wy\clock.rpt
clock

***** Logic for device 'clock' compiled without errors.




Device: EPM7096LC68-7

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF
    MultiVolt I/O                              = OFF

              R              R                    R  R     R  R  
              E              E                    E  E     E  E  
              S              S  V                 S  S     S  S  
              E  7  7     7  E  C                 E  E  V  E  E  
              R  s  s     s  R  C                 R  R  C  R  R  
              V  e  e  G  e  V  I  G  G  G  c  G  V  V  C  V  V  
              E  g  g  N  g  E  N  N  N  N  l  N  E  E  I  E  E  
              D  6  2  D  1  D  T  D  D  D  k  D  D  D  O  D  D  
            -----------------------------------------------------_ 
          /   9  8  7  6  5  4  3  2  1 68 67 66 65 64 63 62 61   | 
RESERVED | 10                                                  60 | RESERVED 
   VCCIO | 11                                                  59 | RESERVED 
 clkscan | 12                                                  58 | GND 
   reset | 13                                                  57 | RESERVED 
    sel0 | 14                                                  56 | RESERVED 
RESERVED | 15                                                  55 | RESERVED 
     GND | 16                                                  54 | RESERVED 
RESERVED | 17                                                  53 | VCCIO 
RESERVED | 18                  EPM7096LC68-7                   52 | RESERVED 
   7seg0 | 19                                                  51 | RESERVED 
   7seg3 | 20                                                  50 | 7seg4 
   VCCIO | 21                                                  49 | 7seg5 
    sel1 | 22                                                  48 | GND 
    sel2 | 23                                                  47 | RESERVED 
RESERVED | 24                                                  46 | RESERVED 
RESERVED | 25                                                  45 | RESERVED 
     GND | 26                                                  44 | RESERVED 
         |_  27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43  _| 
           ------------------------------------------------------ 
              R  R  R  R  V  R  R  G  V  R  R  G  R  R  R  R  V  
              E  E  E  E  C  E  E  N  C  E  E  N  E  E  E  E  C  
              S  S  S  S  C  S  S  D  C  S  S  D  S  S  S  S  C  
              E  E  E  E  I  E  E     I  E  E     E  E  E  E  I  
              R  R  R  R  O  R  R     N  R  R     R  R  R  R  O  
              V  V  V  V     V  V     T  V  V     V  V  V  V     
              E  E  E  E     E  E        E  E     E  E  E  E     
              D  D  D  D     D  D        D  D     D  D  D  D     


N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.



Device-Specific Information:                                   e:\wy\clock.rpt
clock

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16    10/16( 62%)   5/ 8( 62%)  16/16(100%)  34/36( 94%) 
B:    LC17 - LC32    16/16(100%)   5/ 8( 62%)  16/16(100%)  33/36( 91%) 
C:    LC33 - LC48    11/16( 68%)   0/ 8(  0%)  14/16( 87%)  35/36( 97%) 
D:    LC49 - LC64    16/16(100%)   0/ 8(  0%)  16/16(100%)  30/36( 83%) 
E:    LC65 - LC80    16/16(100%)   2/ 8( 25%)  15/16( 93%)  34/36( 94%) 
F:    LC81 - LC96    16/16(100%)   0/ 8(  0%)  12/16( 75%)  35/36( 97%) 


Total dedicated input pins used:                 1/4      ( 25%)
Total I/O pins used:                            12/48     ( 25%)
Total logic cells used:                         85/96     ( 88%)
Total shareable expanders used:                 49/96     ( 51%)
Total Turbo logic cells used:                   85/96     ( 88%)
Total shareable expanders not available (n/a):  40/96     ( 41%)
Average fan-in:                                  11.55
Total fan-in:                                   982

Total input pins required:                       3
Total output pins required:                     10
Total bidirectional pins required:               0
Total logic cells required:                     85
Total flipflops required:                       29
Total product terms required:                  355
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:          42

Synthesized logic cells:                        40/  96   ( 41%)



Device-Specific Information:                                   e:\wy\clock.rpt
clock

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  67      -   -       INPUT  G            0      0   0    0    0    0    0  clk
  12    (4)  (A)      INPUT               0      0   0    0    0    3    0  clkscan
  13    (1)  (A)      INPUT               0      0   0    0    0    3   26  reset


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:                                   e:\wy\clock.rpt
clock