clk7.vhd

来自「ＦＰＧＡ数字钟的设计」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
entity clk7 is
  port (data: in std_logic_vector(3 downto 0);
      doute: out std_logic_vector(6 downto 0));
end clk7;
architecture behave of clk7 is
  begin
process(data)
     begin
      case data is
        when "0000"=>doute<="0111111";
        when "0001"=>doute<="0000110";
        when "0010"=>doute<="1011011";
        when "0011"=>doute<="1001111";
        when "0100"=>doute<="1100110";
        when "0101"=>doute<="1101101";
        when "0110"=>doute<="1111101";
        when "0111"=>doute<="0100111";
        when "1000"=>doute<="1111111";
        when "1001"=>doute<="1101111";
        when others=>doute<="XXXXXXX";
     end case;
  end process;
end behave;