lib.dls

ＦＰＧＡ数字钟的设计

DLSL
1
CLK7.VHDLVIEW U6645366.DLS
CLK7-BEHAV.SYNTHESISVIEW U2692382.DLS
CLK7-BEHAV.VHDLVIEW U8319220.DLS
CLK7-BEHAVE.SYNTHESISVIEW U0159383.DLS
CLK7-BEHAVE.VHDLVIEW U9652668.DLS
M6_1SCAN.VHDLVIEW U2220394.DLS
M6_1SCAN-T1.SYNTHESISVIEW U8268556.DLS
M6_1SCAN-T1.VHDLVIEW U7367137.DLS
NEWHOUR.VHDLVIEW U2715836.DLS
NEWHOUR-T1.SYNTHESISVIEW U6261669.DLS
NEWHOUR-T1.VHDLVIEW U8895855.DLS
NEWMINUTE.VHDLVIEW U2570470.DLS
NEWMINUTE-T1.SYNTHESISVIEW U6337084.DLS
NEWMINUTE-T1.VHDLVIEW U3022476.DLS
NEWSECOND.VHDLVIEW U9328809.DLS
NEWSECOND-T1.SYNTHESISVIEW U8694172.DLS
NEWSECOND-T1.VHDLVIEW U3676661.DLS