newminute.rpt

ＦＰＧＡ数字钟的设计

                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (29)    27    B       SOFT      t        0      0   0    0    2    1    0  |LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node1
 (32)    25    B       SOFT      t        0      0   0    0    4    1    0  |LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node3


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                               e:\wy\newminute.rpt
newminute

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                               Logic cells placed in LAB 'B'
        +--------------------- LC26 carrym
        | +------------------- LC27 |LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node1
        | | +----------------- LC25 |LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node3
        | | | +--------------- LC19 min10
        | | | | +------------- LC18 min11
        | | | | | +----------- LC17 min12
        | | | | | | +--------- LC24 min13
        | | | | | | | +------- LC20 min20
        | | | | | | | | +----- LC23 min21
        | | | | | | | | | +--- LC22 min22
        | | | | | | | | | | +- LC21 min23
        | | | | | | | | | | | 
        | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC27 -> - - - - * - - - - - - | - * | <-- |LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node1
LC25 -> - - - - - - * - - - - | - * | <-- |LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node3
LC19 -> * * * * * * * * * * * | - * | <-- min10
LC18 -> * * * - * * * * * * * | - * | <-- min11
LC17 -> * - * - * * * * * * * | - * | <-- min12
LC24 -> * - * - * - * * * * * | - * | <-- min13
LC20 -> * - - - - - - * * * * | - * | <-- min20
LC23 -> * - - - - - - - * * * | - * | <-- min21
LC22 -> * - - - - - - - * * * | - * | <-- min22
LC21 -> * - - - - - - - * * * | - * | <-- min23

Pin
43   -> - - - - - - - - - - - | - - | <-- carry
4    -> * - - * * * * * * * * | - * | <-- reset


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               e:\wy\newminute.rpt
newminute

** EQUATIONS **

carry    : INPUT;
reset    : INPUT;

-- Node name is 'carrym' = ':11' 
-- Equation name is 'carrym', type is output 
 carrym  = DFFE( _EQ001 $  GND, GLOBAL( carry),  VCC,  VCC, !reset);
  _EQ001 =  min10 & !min11 & !min12 &  min13 &  min20 & !min21 &  min22 & 
             !min23;

-- Node name is 'min10' = 'mint10' 
-- Equation name is 'min10', location is LC019, type is output.
 min10   = TFFE( VCC, GLOBAL( carry), !reset,  VCC,  VCC);

-- Node name is 'min11' = 'mint11' 
-- Equation name is 'min11', location is LC018, type is output.
 min11   = DFFE( _EQ002 $  _LC027, GLOBAL( carry), !reset,  VCC,  VCC);
  _EQ002 =  _LC027 &  min10 & !min11 & !min12 &  min13;

-- Node name is 'min12' = 'mint12' 
-- Equation name is 'min12', location is LC017, type is output.
 min12   = TFFE( _EQ003, GLOBAL( carry), !reset,  VCC,  VCC);
  _EQ003 =  min10 &  min11;

-- Node name is 'min13' = 'mint13' 
-- Equation name is 'min13', location is LC024, type is output.
 min13   = DFFE( _EQ004 $  _LC025, GLOBAL( carry), !reset,  VCC,  VCC);
  _EQ004 =  _LC025 &  min10 & !min11 & !min12 &  min13;

-- Node name is 'min20' = 'mint20' 
-- Equation name is 'min20', location is LC020, type is output.
 min20   = TFFE( _EQ005, GLOBAL( carry), !reset,  VCC,  VCC);
  _EQ005 =  min10 & !min11 & !min12 &  min13;

-- Node name is 'min21' = 'mint21' 
-- Equation name is 'min21', location is LC023, type is output.
 min21   = TFFE( _EQ006, GLOBAL( carry), !reset,  VCC,  VCC);
  _EQ006 =  min10 & !min11 & !min12 &  min13 &  min20 & !min21 &  min23
         #  min10 & !min11 & !min12 &  min13 &  min20 & !min21 & !min22
         #  min10 & !min11 & !min12 &  min13 &  min20 &  min21;

-- Node name is 'min22' = 'mint22' 
-- Equation name is 'min22', location is LC022, type is output.
 min22   = TFFE( _EQ007, GLOBAL( carry), !reset,  VCC,  VCC);
  _EQ007 =  min10 & !min11 & !min12 &  min13 &  min20 & !min21 &  min22 & 
             !min23
         #  min10 & !min11 & !min12 &  min13 &  min20 &  min21;

-- Node name is 'min23' = 'mint23' 
-- Equation name is 'min23', location is LC021, type is output.
 min23   = TFFE( _EQ008, GLOBAL( carry), !reset,  VCC,  VCC);
  _EQ008 =  min10 & !min11 & !min12 &  min13 &  min20 &  min21 &  min22;

-- Node name is '|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC027', type is buried 
_LC027   = LCELL( min11 $  min10);

-- Node name is '|LPM_ADD_SUB:188|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC025', type is buried 
_LC025   = LCELL( min13 $  _EQ009);
  _EQ009 =  min10 &  min11 &  min12;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                        e:\wy\newminute.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 7,189K