tennis.tan.rpt

基于FPGA的乒乓球游戏硬件电路的设计与实现

; N/A           ; None             ; 13.071 ns      ; cou10:ual|lpm_counter:qqout_rtl_1|cntr_2p7:auto_generated|safe_q[1] ; countal[1] ; bain       ;
; N/A           ; None             ; 13.085 ns      ; cou10:ual|lpm_counter:qqout_rtl_1|cntr_2p7:auto_generated|safe_q[0] ; countal[0] ; bain       ;
; N/A           ; None             ; 13.312 ns      ; board:ubdb|serclk                                                   ; speaker    ; bbin       ;
; N/A           ; None             ; 16.622 ns      ; cou10:ubl|lpm_counter:qqout_rtl_3|cntr_2p7:auto_generated|safe_q[0] ; countbl[0] ; bbin       ;
; N/A           ; None             ; 16.623 ns      ; cou10:ubl|lpm_counter:qqout_rtl_3|cntr_2p7:auto_generated|safe_q[3] ; countbl[3] ; bbin       ;
; N/A           ; None             ; 16.625 ns      ; cou10:ubl|lpm_counter:qqout_rtl_3|cntr_2p7:auto_generated|safe_q[2] ; countbl[2] ; bbin       ;
; N/A           ; None             ; 16.664 ns      ; cou10:ubl|lpm_counter:qqout_rtl_3|cntr_2p7:auto_generated|safe_q[1] ; countbl[1] ; bbin       ;
; N/A           ; None             ; 19.197 ns      ; cou4:uah|lpm_counter:qqout_rtl_0|cntr_2p7:auto_generated|safe_q[1]  ; countah[1] ; bain       ;
; N/A           ; None             ; 19.511 ns      ; cou4:uah|lpm_counter:qqout_rtl_0|cntr_2p7:auto_generated|safe_q[0]  ; countah[0] ; bain       ;
; N/A           ; None             ; 19.961 ns      ; cou4:uah|lpm_counter:qqout_rtl_0|cntr_2p7:auto_generated|safe_q[2]  ; countah[2] ; bain       ;
; N/A           ; None             ; 20.276 ns      ; cou4:uah|lpm_counter:qqout_rtl_0|cntr_2p7:auto_generated|safe_q[3]  ; countah[3] ; bain       ;
; N/A           ; None             ; 20.792 ns      ; cou4:ubh|lpm_counter:qqout_rtl_2|cntr_2p7:auto_generated|safe_q[1]  ; countbh[1] ; bbin       ;
; N/A           ; None             ; 21.235 ns      ; cou4:ubh|lpm_counter:qqout_rtl_2|cntr_2p7:auto_generated|safe_q[2]  ; countbh[2] ; bbin       ;
; N/A           ; None             ; 21.237 ns      ; cou4:ubh|lpm_counter:qqout_rtl_2|cntr_2p7:auto_generated|safe_q[3]  ; countbh[3] ; bbin       ;
; N/A           ; None             ; 21.240 ns      ; cou4:ubh|lpm_counter:qqout_rtl_2|cntr_2p7:auto_generated|safe_q[0]  ; countbh[0] ; bbin       ;
+---------------+------------------+----------------+---------------------------------------------------------------------+------------+------------+


+------------------------------------------------------------------------+
; Minimum tpd                                                            ;
+---------------+-------------------+-----------------+--------+---------+
; Minimum Slack ; Required P2P Time ; Actual P2P Time ; From   ; To      ;
+---------------+-------------------+-----------------+--------+---------+
; N/A           ; None              ; 5.045 ns        ; clk    ; lamp    ;
; N/A           ; None              ; 6.987 ns        ; bain   ; speaker ;
; N/A           ; None              ; 7.689 ns        ; souclk ; speaker ;
; N/A           ; None              ; 12.340 ns       ; bbin   ; speaker ;
; N/A           ; None              ; 12.785 ns       ; clr    ; speaker ;
+---------------+-------------------+-----------------+--------+---------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Tue May 10 14:58:58 2005
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off TENNIS -c TENNIS --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clk is an undefined clock
    Info: Assuming node bbin is an undefined clock
    Info: Assuming node bain is an undefined clock
Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock board:ubdb|couclk as buffer
    Info: Detected ripple clock cou10:ubl|cout as buffer
    Info: Detected ripple clock board:ubda|couclk as buffer
    Info: Detected ripple clock cou10:ual|cout as buffer
Info: Clock clk Internal fmax is restricted to 275.03 MHz between source register ball:uball|lamp[8] and destination register ball:uball|lamp[7]
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.290 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y3_N9; Fanout = 4; REG Node = 'ball:uball|lamp[8]'
            Info: 2: + IC(0.552 ns) + CELL(0.738 ns) = 1.290 ns; Loc. = LC_X1_Y3_N3; Fanout = 3; REG Node = 'ball:uball|lamp[7]'
            Info: Total cell delay = 0.738 ns ( 57.21 % )
            Info: Total interconnect delay = 0.552 ns ( 42.79 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock clk to destination register is 2.708 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 11; CLK Node = 'clk'
                Info: 2: + IC(0.528 ns) + CELL(0.711 ns) = 2.708 ns; Loc. = LC_X1_Y3_N3; Fanout = 3; REG Node = 'ball:uball|lamp[7]'
                Info: Total cell delay = 2.180 ns ( 80.50 % )
                Info: Total interconnect delay = 0.528 ns ( 19.50 % )
            Info: - Longest clock path from clock clk to source register is 2.708 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 11; CLK Node = 'clk'
                Info: 2: + IC(0.528 ns) + CELL(0.711 ns) = 2.708 ns; Loc. = LC_X1_Y3_N9; Fanout = 4; REG Node = 'ball:uball|lamp[8]'
                Info: Total cell delay = 2.180 ns ( 80.50 % )
                Info: Total interconnect delay = 0.528 ns ( 19.50 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: Clock bbin Internal fmax is restricted to 275.03 MHz between source register board:ubdb|serclk and destination register board:ubdb|couclk
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 3.081 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y11_N1; Fanout = 2; REG Node = 'board:ubdb|serclk'
            Info: 2: + IC(0.538 ns) + CELL(0.114 ns) = 0.652 ns; Loc. = LC_X16_Y11_N5; Fanout = 2; COMB Node = 'ballctrl:ucpu|ballen~168'
            Info: 3: + IC(0.182 ns) + CELL(0.114 ns) = 0.948 ns; Loc. = LC_X16_Y11_N6; Fanout = 3; COMB Node = 'ballctrl:ucpu|serve~143'
            Info: 4: + IC(0.428 ns) + CELL(0.114 ns) = 1.490 ns; Loc. = LC_X16_Y11_N4; Fanout = 2; COMB Node = 'board:ubdb|couclk~1'
            Info: 5: + IC(0.724 ns) + CELL(0.867 ns) = 3.081 ns; Loc. = LC_X15_Y11_N0; Fanout = 5; REG Node = 'board:ubdb|couclk'
            Info: Total cell delay = 1.209 ns ( 39.24 % )
            Info: Total interconnect delay = 1.872 ns ( 60.76 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock bbin to destination register is 6.939 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_1; Fanout = 5; CLK Node = 'bbin'
                Info: 2: + IC(4.759 ns) + CELL(0.711 ns) = 6.939 ns; Loc. = LC_X15_Y11_N0; Fanout = 5; REG Node = 'board:ubdb|couclk'
                Info: Total cell delay = 2.180 ns ( 31.42 % )
                Info: Total interconnect delay = 4.759 ns ( 68.58 % )
            Info: - Longest clock path from clock bbin to source register is 6.939 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_1; Fanout = 5; CLK Node = 'bbin'
                Info: 2: + IC(4.759 ns) + CELL(0.711 ns) = 6.939 ns; Loc. = LC_X16_Y11_N1; Fanout = 2; REG Node = 'board:ubdb|serclk'
                Info: Total cell delay = 2.180 ns ( 31.42 % )
                Info: Total interconnect delay = 4.759 ns ( 68.58 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: Clock bain Internal fmax is restricted to 275.03 MHz between source register board:ubda|serclk and destination register board:ubda|couclk
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 3.019 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y11_N8; Fanout = 2; REG Node = 'board:ubda|serclk'
            Info: 2: + IC(0.543 ns) + CELL(0.292 ns) = 0.835 ns; Loc.