songer.map.qmsg

基于FPGA的乐曲硬件演奏电路设计的实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 07 14:09:25 2005 " "Info: Processing started: Wed Sep 07 14:09:25 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off SONGER -c SONGER " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off SONGER -c SONGER" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "music.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file music.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 music-SYN " "Info: Found design unit 1: music-SYN" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/music.vhd" "music-SYN" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/music.vhd" 55 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 music " "Info: Found entity 1: music" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/music.vhd" "music" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/music.vhd" 45 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "notetabs.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file notetabs.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 NoteTabs-one " "Info: Found design unit 1: NoteTabs-one" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/notetabs.vhd" "NoteTabs-one" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/notetabs.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 NoteTabs " "Info: Found entity 1: NoteTabs" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/notetabs.vhd" "NoteTabs" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/notetabs.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SONGER.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file SONGER.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Songer-one " "Info: Found design unit 1: Songer-one" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.vhd" "Songer-one" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 Songer " "Info: Found entity 1: Songer" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.vhd" "Songer" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "speakera.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file speakera.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Speakera-one " "Info: Found design unit 1: Speakera-one" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/speakera.vhd" "Speakera-one" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/speakera.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 Speakera " "Info: Found entity 1: Speakera" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/speakera.vhd" "Speakera" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/speakera.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "tonetaba.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file tonetaba.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ToneTaba-one " "Info: Found design unit 1: ToneTaba-one" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" "ToneTaba-one" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 ToneTaba " "Info: Found entity 1: ToneTaba" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" "ToneTaba" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus41/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "e:/altera/quartus41/libraries/megafunctions/altsyncram.tdf" "altsyncram" "" { Text "e:/altera/quartus41/libraries/megafunctions/altsyncram.tdf" 431 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_des.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_des.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_des " "Info: Found entity 1: altsyncram_des" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/altsyncram_des.tdf" "altsyncram_des" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/altsyncram_des.tdf" 33 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_j6a2.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_j6a2.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_j6a2 " "Info: Found entity 1: altsyncram_j6a2" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/altsyncram_j6a2.tdf" "altsyncram_j6a2" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/altsyncram_j6a2.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_mod_ram_rom_pack " "Info: Found design unit 1: sld_mod_ram_rom_pack" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "sld_mod_ram_rom_pack" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 4 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_mod_ram_rom-rtl " "Info: Found design unit 2: sld_mod_ram_rom-rtl" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "sld_mod_ram_rom-rtl" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 72 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_mod_ram_rom " "Info: Found entity 1: sld_mod_ram_rom" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" "sld_mod_ram_rom" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_mod_ram_rom.vhd" 16 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_rom_sr-INFO_REG " "Info: Found design unit 1: sld_rom_sr-INFO_REG" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" "sld_rom_sr-INFO_REG" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" 27 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_rom_sr " "Info: Found entity 1: sld_rom_sr" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" "sld_rom_sr" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_rom_sr.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "tone tonetaba.vhd(11) " "Warning: VHDL Process Statement warning at tonetaba.vhd(11): signal or variable tone may not be assigned a new value in every possible path through the Process Statement. Signal or variable tone holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" 11 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "code tonetaba.vhd(11) " "Warning: VHDL Process Statement warning at tonetaba.vhd(11): signal or variable code may not be assigned a new value in every possible path through the Process Statement. Signal or variable code holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" 11 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "high tonetaba.vhd(11) " "Warning: VHDL Process Statement warning at tonetaba.vhd(11): signal or variable high may not be assigned a new value in every possible path through the Process Statement. Signal or variable high holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/tonetaba.vhd" 11 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd 6 2 " "Info: Found 6 design units, including 2 entities, in source file e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 HUB_PACK " "Info: Found design unit 1: HUB_PACK" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "HUB_PACK" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 49 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 JTAG_PACK " "Info: Found design unit 2: JTAG_PACK" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "JTAG_PACK" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 63 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 sld_hub-rtl " "Info: Found design unit 3: sld_hub-rtl" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "sld_hub-rtl" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 166 -1 0 } }  } 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 sld_jtag_state_machine-rtl " "Info: Found design unit 4: sld_jtag_state_machine-rtl" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "sld_jtag_state_machine-rtl" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 1012 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_hub " "Info: Found entity 1: sld_hub" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "sld_hub" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 99 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_jtag_state_machine " "Info: Found entity 2: sld_jtag_state_machine" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "sld_jtag_state_machine" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 997 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus41/libraries/megafunctions/lpm_shiftreg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus41/libraries/megafunctions/lpm_shiftreg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_shiftreg " "Info: Found entity 1: lpm_shiftreg" {  } { { "e:/altera/quartus41/libraries/megafunctions/lpm_shiftreg.tdf" "lpm_shiftreg" "" { Text "e:/altera/quartus41/libraries/megafunctions/lpm_shiftreg.tdf" 43 1 0 } }  } 0}  } {  } 0}