songer.tan.qmsg

基于FPGA的乐曲硬件演奏电路设计的实现

{ "Info" "ITDB_TSU_RESULT" "sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\] altera_internal_jtag~TMSUTAP altera_internal_jtag~TCKUTAP -0.626 ns register " "Info: tsu for register sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\] (data pin = altera_internal_jtag~TMSUTAP, clock pin = altera_internal_jtag~TCKUTAP) is -0.626 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.182 ns + Longest pin register " "Info: + Longest pin to register delay is 4.182 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TMSUTAP 1 PIN JTAG_X1_Y6_N1 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 23; PIN Node = 'altera_internal_jtag~TMSUTAP'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TMSUTAP } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.904 ns) + CELL(0.114 ns) 2.018 ns sld_hub:sld_hub_inst\|IRF_ENA_ENABLE~21 2 COMB LC_X12_Y6_N4 2 " "Info: 2: + IC(1.904 ns) + CELL(0.114 ns) = 2.018 ns; Loc. = LC_X12_Y6_N4; Fanout = 2; COMB Node = 'sld_hub:sld_hub_inst\|IRF_ENA_ENABLE~21'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "2.018 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 371 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.297 ns) + CELL(0.867 ns) 4.182 ns sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\] 3 REG LC_X11_Y4_N5 3 " "Info: 3: + IC(1.297 ns) + CELL(0.867 ns) = 4.182 ns; Loc. = LC_X11_Y4_N5; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\]'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "2.164 ns" { sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.981 ns 23.46 % " "Info: Total cell delay = 0.981 ns ( 23.46 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.201 ns 76.54 % " "Info: Total interconnect delay = 3.201 ns ( 76.54 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "4.182 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.845 ns - Shortest register " "Info: - Shortest clock path from clock altera_internal_jtag~TCKUTAP to destination register is 4.845 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 117 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 117; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.134 ns) + CELL(0.711 ns) 4.845 ns sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\] 2 REG LC_X11_Y4_N5 3 " "Info: 2: + IC(4.134 ns) + CELL(0.711 ns) = 4.845 ns; Loc. = LC_X11_Y4_N5; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\]'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "4.845 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_dffex.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 14.67 % " "Info: Total cell delay = 0.711 ns ( 14.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.134 ns 85.33 % " "Info: Total interconnect delay = 4.134 ns ( 85.33 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "4.845 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } } }  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "4.182 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "4.845 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK8HZ CODE1\[2\] NoteTabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_des:auto_generated\|altsyncram_j6a2:altsyncram1\|ram_block3a2~porta_address_reg0 16.740 ns memory " "Info: tco from clock CLK8HZ to destination pin CODE1\[2\] through memory NoteTabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_des:auto_generated\|altsyncram_j6a2:altsyncram1\|ram_block3a2~porta_address_reg0 is 16.740 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK8HZ source 2.732 ns + Longest memory " "Info: + Longest clock path from clock CLK8HZ to source memory is 2.732 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK8HZ 1 CLK PIN_17 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 25; CLK Node = 'CLK8HZ'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "" { CLK8HZ } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.541 ns) + CELL(0.722 ns) 2.732 ns NoteTabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_des:auto_generated\|altsyncram_j6a2:altsyncram1\|ram_block3a2~porta_address_reg0 2 MEM M4K_X13_Y4 4 " "Info: 2: + IC(0.541 ns) + CELL(0.722 ns) = 2.732 ns; Loc. = M4K_X13_Y4; Fanout = 4; MEM Node = 'NoteTabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_des:auto_generated\|altsyncram_j6a2:altsyncram1\|ram_block3a2~porta_address_reg0'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "1.263 ns" { CLK8HZ NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|ram_block3a2~porta_address_reg0 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/altsyncram_j6a2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/altsyncram_j6a2.tdf" 107 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 80.20 % " "Info: Total cell delay = 2.191 ns ( 80.20 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.541 ns 19.80 % " "Info: Total interconnect delay = 0.541 ns ( 19.80 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "2.732 ns" { CLK8HZ NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|ram_block3a2~porta_address_reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/altsyncram_j6a2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/altsyncram_j6a2.tdf" 107 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.358 ns + Longest memory pin " "Info: + Longest memory to pin delay is 13.358 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns NoteTabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_des:auto_generated\|altsyncram_j6a2:altsyncram1\|ram_block3a2~porta_address_reg0 1 MEM M4K_X13_Y4 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y4; Fanout = 4; MEM Node = 'NoteTabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_des:auto_generated\|altsyncram_j6a2:altsyncram1\|ram_block3a2~porta_address_reg0'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "" { NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|ram_block3a2~porta_address_reg0 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/altsyncram_j6a2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/altsyncram_j6a2.tdf" 107 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.308 ns) 4.308 ns NoteTabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_des:auto_generated\|altsyncram_j6a2:altsyncram1\|q_a\[3\] 2 MEM M4K_X13_Y4 16 " "Info: 2: + IC(0.000 ns) + CELL(4.308 ns) = 4.308 ns; Loc. = M4K_X13_Y4; Fanout = 16; MEM Node = 'NoteTabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_des:auto_generated\|altsyncram_j6a2:altsyncram1\|q_a\[3\]'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "4.308 ns" { NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|ram_block3a2~porta_address_reg0 NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|q_a[3] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/altsyncram_j6a2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/altsyncram_j6a2.tdf" 38 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.871 ns) + CELL(0.442 ns) 6.621 ns ToneTaba:u2\|Mux~121 3 COMB LC_X5_Y4_N9 15 " "Info: 3: + IC(1.871 ns) + CELL(0.442 ns) = 6.621 ns; Loc. = LC_X5_Y4_N9; Fanout = 15; COMB Node = 'ToneTaba:u2\|Mux~121'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "2.313 ns" { NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|q_a[3] ToneTaba:u2|Mux~121 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.865 ns) + CELL(0.590 ns) 9.076 ns ToneTaba:u2\|CODE\[2\]~458 4 COMB LC_X8_Y8_N2 2 " "Info: 4: + IC(1.865 ns) + CELL(0.590 ns) = 9.076 ns; Loc. = LC_X8_Y8_N2; Fanout = 2; COMB Node = 'ToneTaba:u2\|CODE\[2\]~458'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6de