songer.tan.qmsg

基于FPGA的乐曲硬件演奏电路设计的实现

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 register sld_hub:sld_hub_inst\|HUB_TDO~reg0 128.17 MHz 7.802 ns Internal " "Info: Clock altera_internal_jtag~TCKUTAP has Internal fmax of 128.17 MHz between source register sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 and destination register sld_hub:sld_hub_inst\|HUB_TDO~reg0 (period= 7.802 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.642 ns + Longest register register " "Info: + Longest register to register delay is 3.642 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 1 REG LC_X8_Y7_N9 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y7_N9; Fanout = 14; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 505 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.258 ns) + CELL(0.442 ns) 1.700 ns sld_hub:sld_hub_inst\|HUB_TDO~364 2 COMB LC_X10_Y7_N5 1 " "Info: 2: + IC(1.258 ns) + CELL(0.442 ns) = 1.700 ns; Loc. = LC_X10_Y7_N5; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|HUB_TDO~364'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "1.700 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_hub:sld_hub_inst|HUB_TDO~364 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.633 ns) + CELL(0.309 ns) 3.642 ns sld_hub:sld_hub_inst\|HUB_TDO~reg0 3 REG LC_X12_Y6_N9 0 " "Info: 3: + IC(1.633 ns) + CELL(0.309 ns) = 3.642 ns; Loc. = LC_X12_Y6_N9; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|HUB_TDO~reg0'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "1.942 ns" { sld_hub:sld_hub_inst|HUB_TDO~364 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.751 ns 20.62 % " "Info: Total cell delay = 0.751 ns ( 20.62 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.891 ns 79.38 % " "Info: Total interconnect delay = 2.891 ns ( 79.38 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "3.642 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_hub:sld_hub_inst|HUB_TDO~364 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.002 ns - Smallest " "Info: - Smallest clock skew is 0.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.856 ns + Shortest register " "Info: + Shortest clock path from clock altera_internal_jtag~TCKUTAP to destination register is 4.856 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 117 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 117; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.145 ns) + CELL(0.711 ns) 4.856 ns sld_hub:sld_hub_inst\|HUB_TDO~reg0 2 REG LC_X12_Y6_N9 0 " "Info: 2: + IC(4.145 ns) + CELL(0.711 ns) = 4.856 ns; Loc. = LC_X12_Y6_N9; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|HUB_TDO~reg0'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "4.856 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 14.64 % " "Info: Total cell delay = 0.711 ns ( 14.64 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.145 ns 85.36 % " "Info: Total interconnect delay = 4.145 ns ( 85.36 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "4.856 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 4.854 ns - Longest register " "Info: - Longest clock path from clock altera_internal_jtag~TCKUTAP to source register is 4.854 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 117 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 117; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.143 ns) + CELL(0.711 ns) 4.854 ns sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 2 REG LC_X8_Y7_N9 14 " "Info: 2: + IC(4.143 ns) + CELL(0.711 ns) = 4.854 ns; Loc. = LC_X8_Y7_N9; Fanout = 14; REG Node = 'sld_hub:sld_hub_inst\|jtag_debug_mode_usr1'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "4.854 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 505 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 14.65 % " "Info: Total cell delay = 0.711 ns ( 14.65 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.143 ns 85.35 % " "Info: Total interconnect delay = 4.143 ns ( 85.35 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "4.854 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } }  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "4.856 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "4.854 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 505 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 505 -1 0 } } { "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" "" "" { Text "e:/altera/quartus41/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } }  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "3.642 ns" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 sld_hub:sld_hub_inst|HUB_TDO~364 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "4.856 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "4.854 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK8HZ memory NoteTabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_des:auto_generated\|altsyncram_j6a2:altsyncram1\|ram_block3a2~porta_datain_reg3 memory NoteTabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_des:auto_generated\|altsyncram_j6a2:altsyncram1\|ram_block3a2~porta_memory_reg3 197.01 MHz 5.076 ns Internal " "Info: Clock CLK8HZ has Internal fmax of 197.01 MHz between source memory NoteTabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_des:auto_generated\|altsyncram_j6a2:altsyncram1\|ram_block3a2~porta_datain_reg3 and destination memory NoteTabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_des:auto_generated\|altsyncram_j6a2:altsyncram1\|ram_block3a2~porta_memory_reg3 (period= 5.076 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns + Longest memory memory " "Info: + Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns NoteTabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_des:auto_generated\|altsyncram_j6a2:altsyncram1\|ram_block3a2~porta_datain_reg3 1 MEM M4K_X13_Y4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y4; Fanout = 1; MEM Node = 'NoteTabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_des:auto_generated\|altsyncram_j6a2:altsyncram1\|ram_block3a2~porta_datain_reg3'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "" { NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|ram_block3a2~porta_datain_reg3 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/altsyncram_j6a2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/altsyncram_j6a2.tdf" 107 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns NoteTabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_des:auto_generated\|altsyncram_j6a2:altsyncram1\|ram_block3a2~porta_memory_reg3 2 MEM M4K_X13_Y4 0 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X13_Y4; Fanout = 0; MEM Node = 'NoteTabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_des:auto_generated\|altsyncram_j6a2:altsyncram1\|ram_block3a2~porta_memory_reg3'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "4.319 ns" { NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|ram_block3a2~porta_datain_reg3 NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|ram_block3a2~porta_memory_reg3 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/altsyncram_j6a2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/altsyncram_j6a2.tdf" 107 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns 100.00 % " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "4.319 ns" { NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|ram_block3a2~porta_datain_reg3 NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|ram_block3a2~porta_memory_reg3 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns - Smallest " "Info: - Smallest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK8HZ destination 2.718 ns + Shortest memory " "Info: + Shortest clock path from clock CLK8HZ to destination memory is 2.718 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK8HZ 1 CLK PIN_17 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 25; CLK Node = 'CLK8HZ'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "" { CLK8HZ } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.541 ns) + CELL(0.708 ns) 2.718 ns NoteTabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_des:auto_generated\|altsyncram_j6a2:altsyncram1\|ram_block3a2~porta_memory_reg3 2 MEM M4K_X13_Y4 0 " "Info: 2: + IC(0.541 ns) + CELL(0.708 ns) = 2.718 ns; Loc. = M4K_X13_Y4; Fanout = 0; MEM Node = 'NoteTabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_des:auto_generated\|altsyncram_j6a2:altsyncram1\|ram_block3a2~porta_memory_reg3'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "1.249 ns" { CLK8HZ NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|ram_block3a2~porta_memory_reg3 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/altsyncram_j6a2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/altsyncram_j6a2.tdf" 107 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.177 ns 80.10 % " "Info: Total cell delay = 2.177 ns ( 80.10 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.541 ns 19.90 % " "Info: Total interconnect delay = 0.541 ns ( 19.90 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "2.718 ns" { CLK8HZ NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|ram_block3a2~porta_memory_reg3 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK8HZ source 2.732 ns - Longest memory " "Info: - Longest clock path from clock CLK8HZ to source memory is 2.732 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK8HZ 1 CLK PIN_17 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 25; CLK Node = 'CLK8HZ'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "" { CLK8HZ } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.541 ns) + CELL(0.722 ns) 2.732 ns NoteTabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_des:auto_generated\|altsyncram_j6a2:altsyncram1\|ram_block3a2~porta_datain_reg3 2 MEM M4K_X13_Y4 1 " "Info: 2: + IC(0.541 ns) + CELL(0.722 ns) = 2.732 ns; Loc. = M4K_X13_Y4; Fanout = 1; MEM Node = 'NoteTabs:u1\|music:u1\|altsyncram:altsyncram_component\|altsyncram_des:auto_generated\|altsyncram_j6a2:altsyncram1\|ram_block3a2~porta_datain_reg3'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "1.263 ns" { CLK8HZ NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|ram_block3a2~porta_datain_reg3 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/altsyncram_j6a2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/altsyncram_j6a2.tdf" 107 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.191 ns 80.20 % " "Info: Total cell delay = 2.191 ns ( 80.20 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.541 ns 19.80 % " "Info: Total interconnect delay = 0.541 ns ( 19.80 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "2.732 ns" { CLK8HZ NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|ram_block3a2~porta_datain_reg3 } "NODE_NAME" } } }  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "2.718 ns" { CLK8HZ NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|ram_block3a2~porta_memory_reg3 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "2.732 ns" { CLK8HZ NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|ram_block3a2~porta_datain_reg3 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns + " "Info: + Micro clock to output delay of source is 0.650 ns" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/altsyncram_j6a2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/altsyncram_j6a2.tdf" 107 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns + " "Info: + Micro setup delay of destination is 0.093 ns" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/altsyncram_j6a2.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/altsyncram_j6a2.tdf" 107 2 0 } }  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "4.319 ns" { NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|ram_block3a2~porta_datain_reg3 NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|ram_block3a2~porta_memory_reg3 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "2.718 ns" { CLK8HZ NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|ram_block3a2~porta_memory_reg3 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "2.732 ns" { CLK8HZ NoteTabs:u1|music:u1|altsyncram:altsyncram_component|altsyncram_des:auto_generated|altsyncram_j6a2:altsyncram1|ram_block3a2~porta_datain_reg3 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK12MHZ register Speakera:u3\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_1\|cntr_7t7:auto_generated\|safe_q\[4\] register Speakera:u3\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_1\|cntr_7t7:auto_generated\|safe_q\[4\] 187.34 MHz 5.338 ns Internal " "Info: Clock CLK12MHZ has Internal fmax of 187.34 MHz between source register Speakera:u3\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_1\|cntr_7t7:auto_generated\|safe_q\[4\] and destination register Speakera:u3\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_1\|cntr_7t7:auto_generated\|safe_q\[4\] (period= 5.338 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.074 ns + Longest register register " "Info: + Longest register to register delay is 5.074 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Speakera:u3\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_1\|cntr_7t7:auto_generated\|safe_q\[4\] 1 REG LC_X5_Y10_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y10_N9; Fanout = 3; REG Node = 'Speakera:u3\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_1\|cntr_7t7:auto_generated\|safe_q\[4\]'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "" { Speakera:u3|lpm_counter:\GenSpkS:Count11[0]_rtl_1|cntr_7t7:auto_generated|safe_q[4] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_7t7.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_7t7.tdf" 133 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.126 ns) + CELL(0.442 ns) 1.568 ns Speakera:u3\|reduce_nor~69 2 COMB LC_X5_Y9_N6 2 " "Info: 2: + IC(1.126 ns) + CELL(0.442 ns) = 1.568 ns; Loc. = LC_X5_Y9_N6; Fanout = 2; COMB Node = 'Speakera:u3\|reduce_nor~69'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "1.568 ns" { Speakera:u3|lpm_counter:\GenSpkS:Count11[0]_rtl_1|cntr_7t7:auto_generated|safe_q[4] Speakera:u3|reduce_nor~69 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.590 ns) 2.595 ns Speakera:u3\|reduce_nor~71 3 COMB LC_X5_Y9_N8 11 " "Info: 3: + IC(0.437 ns) + CELL(0.590 ns) = 2.595 ns; Loc. = LC_X5_Y9_N8; Fanout = 11; COMB Node = 'Speakera:u3\|reduce_nor~71'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "1.027 ns" { Speakera:u3|reduce_nor~69 Speakera:u3|reduce_nor~71 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.254 ns) + CELL(1.225 ns) 5.074 ns Speakera:u3\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_1\|cntr_7t7:auto_generated\|safe_q\[4\] 4 REG LC_X5_Y10_N9 3 " "Info: 4: + IC(1.254 ns) + CELL(1.225 ns) = 5.074 ns; Loc. = LC_X5_Y10_N9; Fanout = 3; REG Node = 'Speakera:u3\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_1\|cntr_7t7:auto_generated\|safe_q\[4\]'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "2.479 ns" { Speakera:u3|reduce_nor~71 Speakera:u3|lpm_counter:\GenSpkS:Count11[0]_rtl_1|cntr_7t7:auto_generated|safe_q[4] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_7t7.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_7t7.tdf" 133 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.257 ns 44.48 % " "Info: Total cell delay = 2.257 ns ( 44.48 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.817 ns 55.52 % " "Info: Total interconnect delay = 2.817 ns ( 55.52 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "5.074 ns" { Speakera:u3|lpm_counter:\GenSpkS:Count11[0]_rtl_1|cntr_7t7:auto_generated|safe_q[4] Speakera:u3|reduce_nor~69 Speakera:u3|reduce_nor~71 Speakera:u3|lpm_counter:\GenSpkS:Count11[0]_rtl_1|cntr_7t7:auto_generated|safe_q[4] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.003 ns - Smallest " "Info: - Smallest clock skew is -0.003 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK12MHZ destination 8.424 ns + Shortest register " "Info: + Shortest clock path from clock CLK12MHZ to destination register is 8.424 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK12MHZ 1 CLK PIN_92 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_92; Fanout = 4; CLK Node = 'CLK12MHZ'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "" { CLK12MHZ } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.565 ns) + CELL(0.935 ns) 2.969 ns Speakera:u3\|lpm_counter:\\DivideCLK:Count4\[0\]_rtl_2\|cntr_ea7:auto_generated\|safe_q\[3\] 2 REG LC_X6_Y10_N9 2 " "Info: 2: + IC(0.565 ns) + CELL(0.935 ns) = 2.969 ns; Loc. = LC_X6_Y10_N9; Fanout = 2; REG Node = 'Speakera:u3\|lpm_counter:\\DivideCLK:Count4\[0\]_rtl_2\|cntr_ea7:auto_generated\|safe_q\[3\]'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "1.500 ns" { CLK12MHZ Speakera:u3|lpm_counter:\DivideCLK:Count4[0]_rtl_2|cntr_ea7:auto_generated|safe_q[3] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_ea7.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_ea7.tdf" 76 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.557 ns) + CELL(0.292 ns) 3.818 ns Speakera:u3\|PreCLK~15 3 COMB LC_X6_Y10_N5 16 " "Info: 3: + IC(0.557 ns) + CELL(0.292 ns) = 3.818 ns; Loc. = LC_X6_Y10_N5; Fanout = 16; COMB Node = 'Speakera:u3\|PreCLK~15'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "0.849 ns" { Speakera:u3|lpm_counter:\DivideCLK:Count4[0]_rtl_2|cntr_ea7:auto_generated|safe_q[3] Speakera:u3|PreCLK~15 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/speakera.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/speakera.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.895 ns) + CELL(0.711 ns) 8.424 ns Speakera:u3\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_1\|cntr_7t7:auto_generated\|safe_q\[4\] 4 REG LC_X5_Y10_N9 3 " "Info: 4: + IC(3.895 ns) + CELL(0.711 ns) = 8.424 ns; Loc. = LC_X5_Y10_N9; Fanout = 3; REG Node = 'Speakera:u3\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_1\|cntr_7t7:auto_generated\|safe_q\[4\]'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "4.606 ns" { Speakera:u3|PreCLK~15 Speakera:u3|lpm_counter:\GenSpkS:Count11[0]_rtl_1|cntr_7t7:auto_generated|safe_q[4] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_7t7.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_7t7.tdf" 133 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.407 ns 40.44 % " "Info: Total cell delay = 3.407 ns ( 40.44 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.017 ns 59.56 % " "Info: Total interconnect delay = 5.017 ns ( 59.56 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "8.424 ns" { CLK12MHZ Speakera:u3|lpm_counter:\DivideCLK:Count4[0]_rtl_2|cntr_ea7:auto_generated|safe_q[3] Speakera:u3|PreCLK~15 Speakera:u3|lpm_counter:\GenSpkS:Count11[0]_rtl_1|cntr_7t7:auto_generated|safe_q[4] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK12MHZ source 8.427 ns - Longest register " "Info: - Longest clock path from clock CLK12MHZ to source register is 8.427 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLK12MHZ 1 CLK PIN_92 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_92; Fanout = 4; CLK Node = 'CLK12MHZ'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "" { CLK12MHZ } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.vhd" 4 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.565 ns) + CELL(0.935 ns) 2.969 ns Speakera:u3\|lpm_counter:\\DivideCLK:Count4\[0\]_rtl_2\|cntr_ea7:auto_generated\|safe_q\[2\] 2 REG LC_X6_Y10_N8 4 " "Info: 2: + IC(0.565 ns) + CELL(0.935 ns) = 2.969 ns; Loc. = LC_X6_Y10_N8; Fanout = 4; REG Node = 'Speakera:u3\|lpm_counter:\\DivideCLK:Count4\[0\]_rtl_2\|cntr_ea7:auto_generated\|safe_q\[2\]'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "1.500 ns" { CLK12MHZ Speakera:u3|lpm_counter:\DivideCLK:Count4[0]_rtl_2|cntr_ea7:auto_generated|safe_q[2] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_ea7.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_ea7.tdf" 76 8 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.738 ns) + CELL(0.114 ns) 3.821 ns Speakera:u3\|PreCLK~15 3 COMB LC_X6_Y10_N5 16 " "Info: 3: + IC(0.738 ns) + CELL(0.114 ns) = 3.821 ns; Loc. = LC_X6_Y10_N5; Fanout = 16; COMB Node = 'Speakera:u3\|PreCLK~15'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "0.852 ns" { Speakera:u3|lpm_counter:\DivideCLK:Count4[0]_rtl_2|cntr_ea7:auto_generated|safe_q[2] Speakera:u3|PreCLK~15 } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/speakera.vhd" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/speakera.vhd" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.895 ns) + CELL(0.711 ns) 8.427 ns Speakera:u3\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_1\|cntr_7t7:auto_generated\|safe_q\[4\] 4 REG LC_X5_Y10_N9 3 " "Info: 4: + IC(3.895 ns) + CELL(0.711 ns) = 8.427 ns; Loc. = LC_X5_Y10_N9; Fanout = 3; REG Node = 'Speakera:u3\|lpm_counter:\\GenSpkS:Count11\[0\]_rtl_1\|cntr_7t7:auto_generated\|safe_q\[4\]'" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "4.606 ns" { Speakera:u3|PreCLK~15 Speakera:u3|lpm_counter:\GenSpkS:Count11[0]_rtl_1|cntr_7t7:auto_generated|safe_q[4] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_7t7.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_7t7.tdf" 133 8 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.229 ns 38.32 % " "Info: Total cell delay = 3.229 ns ( 38.32 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.198 ns 61.68 % " "Info: Total interconnect delay = 5.198 ns ( 61.68 % )" {  } {  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "8.427 ns" { CLK12MHZ Speakera:u3|lpm_counter:\DivideCLK:Count4[0]_rtl_2|cntr_ea7:auto_generated|safe_q[2] Speakera:u3|PreCLK~15 Speakera:u3|lpm_counter:\GenSpkS:Count11[0]_rtl_1|cntr_7t7:auto_generated|safe_q[4] } "NODE_NAME" } } }  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "8.424 ns" { CLK12MHZ Speakera:u3|lpm_counter:\DivideCLK:Count4[0]_rtl_2|cntr_ea7:auto_generated|safe_q[3] Speakera:u3|PreCLK~15 Speakera:u3|lpm_counter:\GenSpkS:Count11[0]_rtl_1|cntr_7t7:auto_generated|safe_q[4] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "8.427 ns" { CLK12MHZ Speakera:u3|lpm_counter:\DivideCLK:Count4[0]_rtl_2|cntr_ea7:auto_generated|safe_q[2] Speakera:u3|PreCLK~15 Speakera:u3|lpm_counter:\GenSpkS:Count11[0]_rtl_1|cntr_7t7:auto_generated|safe_q[4] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_7t7.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_7t7.tdf" 133 8 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_7t7.tdf" "" "" { Text "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/cntr_7t7.tdf" 133 8 0 } }  } 0}  } { { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "5.074 ns" { Speakera:u3|lpm_counter:\GenSpkS:Count11[0]_rtl_1|cntr_7t7:auto_generated|safe_q[4] Speakera:u3|reduce_nor~69 Speakera:u3|reduce_nor~71 Speakera:u3|lpm_counter:\GenSpkS:Count11[0]_rtl_1|cntr_7t7:auto_generated|safe_q[4] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "8.424 ns" { CLK12MHZ Speakera:u3|lpm_counter:\DivideCLK:Count4[0]_rtl_2|cntr_ea7:auto_generated|safe_q[3] Speakera:u3|PreCLK~15 Speakera:u3|lpm_counter:\GenSpkS:Count11[0]_rtl_1|cntr_7t7:auto_generated|safe_q[4] } "NODE_NAME" } } } { "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" "" "" { Report "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER_cmp.qrpt" Compiler "SONGER" "UNKNOWN" "V1" "H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/db/SONGER.quartus_db" { Floorplan "" "" "8.427 ns" { CLK12MHZ Speakera:u3|lpm_counter:\DivideCLK:Count4[0]_rtl_2|cntr_ea7:auto_generated|safe_q[2] Speakera:u3|PreCLK~15 Speakera:u3|lpm_counter:\GenSpkS:Count11[0]_rtl_1|cntr_7t7:auto_generated|safe_q[4] } "NODE_NAME" } } }  } 0}