songer.fit.rpt

基于FPGA的乐曲硬件演奏电路设计的实现

; Auto Merge PLLs                                    ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic ; Off                            ; Off                            ;
; Perform Register Duplication                       ; Off                            ; Off                            ;
; Perform Register Retiming                          ; Off                            ; Off                            ;
; Physical Synthesis Effort Level                    ; Normal                         ; Normal                         ;
; Logic Cell Insertion -- Logic Duplication          ; Auto                           ; Auto                           ;
; Auto Register Duplication                          ; Off                            ; Off                            ;
; Auto Global Clock                                  ; On                             ; On                             ;
; Auto Global Register Control Signals               ; On                             ; On                             ;
+----------------------------------------------------+--------------------------------+--------------------------------+


+----------------------------------------------------------------------------------------+
; Fitter Device Options                                                                  ;
+----------------------------------------------+-----------------------------------------+
; Option                                       ; Setting                                 ;
+----------------------------------------------+-----------------------------------------+
; Auto-restart configuration after error       ; On                                      ;
; Release clears before tri-states             ; Off                                     ;
; Enable user-supplied start-up clock (CLKUSR) ; Off                                     ;
; Enable device-wide reset (DEV_CLRn)          ; Off                                     ;
; Enable device-wide output enable (DEV_OE)    ; Off                                     ;
; Enable INIT_DONE output                      ; Off                                     ;
; Configuration scheme                         ; Active Serial                           ;
; Reserve ASDO pin after configuration.        ; As output driving an unspecified signal ;
; Reserve all unused pins                      ; As output driving ground                ;
; Base pin-out file on sameframe device        ; Off                                     ;
+----------------------------------------------+-----------------------------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.fit.eqn.


+----------------+
; Floorplan View ;
+----------------+
Floorplan report data cannot be output to ASCII.
Please use Quartus II to view the floorplan report data.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in H:/ZX1C3_1C6demo/EDA_VHDL_1C3/Chapter10/EP1C3_10_1_SONGER/SONGER.pin.


+-----------------------------------------------------------+
; Fitter Resource Usage Summary                             ;
+--------------------------------+--------------------------+
; Resource                       ; Usage                    ;
+--------------------------------+--------------------------+
; Logic cells                    ; 218 / 2,910 ( 7 % )      ;
; Registers                      ; 125 / 3,210 ( 3 % )      ;
; Total LABs                     ; 27 / 291 ( 9 % )         ;
; Logic elements in carry chains ; 41                       ;
; User inserted logic cells      ; 0                        ;
; Virtual pins                   ; 0                        ;
; I/O pins                       ; 8 / 104 ( 7 % )          ;
;     -- Clock pins              ; 0 / 2 ( 0 % )            ;
; Global signals                 ; 8                        ;
; M4Ks                           ; 1 / 13 ( 7 % )           ;
; Total memory bits              ; 1,024 / 59,904 ( 1 % )   ;
; Total RAM block bits           ; 4,608 / 59,904 ( 7 % )   ;
; Global clocks                  ; 8 / 8 ( 100 % )          ;
; Maximum fan-out node           ; altera_internal_jtag~TDO ;
; Maximum fan-out                ; 107                      ;
; Total fan-out                  ; 927                      ;
; Average fan-out                ; 3.96                     ;
+--------------------------------+--------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                     ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; CLK12MHZ ; 92    ; 3        ; 27           ; 8            ; 4           ; 4                     ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; User                 ;
; CLK8HZ   ; 17    ; 1        ; 0            ; 7            ; 0           ; 9                     ; 0                  ; yes    ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; User                 ;
+----------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                         ;
+----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+
; Name     ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ;
+----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+
; CODE1[0] ; 39    ; 4        ; 4            ; 0            ; 1           ; no              ; no                     ; no            ; no             ; no              ; no         ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; User                 ;
; CODE1[1] ; 40    ; 4        ; 4            ; 0            ; 0           ; no              ; no                     ; no            ; no             ; no              ; no         ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; User                 ;
; CODE1[2] ; 41    ; 4        ; 6            ; 0            ; 1           ; no              ; no                     ; no            ; no             ; no              ; no         ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; User                 ;
; CODE1[3] ; 42    ; 4        ; 6            ; 0            ; 0           ; no              ; no                     ; no            ; no             ; no              ; no         ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; User                 ;
; HIGH1    ; 11    ; 1        ; 0            ; 9            ; 0           ; no              ; no                     ; no            ; no             ; no              ; no         ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; User                 ;
; SPKOUT   ; 129   ; 2        ; 12           ; 14           ; 2           ; no              ; no                     ; no            ; no             ; no              ; no         ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; User                 ;
+----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+----------+--------------+--------------+------------------+-------------+----------------------+


+-----------------------------------------------------------+