lwbdecode.v

vhdl,用i2c控制philips的7111和7128

/////////////////////////////////////////////////////////////////////
////                                                             ////
////             LWB rev 1.2 -- Memory Address Decode            ////
////                                                             ////
////                                                             ////
////                 Author: Liu Tao                             ////
////          [e-mail]                           ////
////                                                             ////
////                                                             ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2003 Liu Tao                                  ////
////               [e-mail]                      ////
////                                                             ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
`include "timescale.v"

module LWBDECODE(reset,CE3_,ARE_,AWE_,EA,ED_I,ED_SRAM,ED_OEN_O,ED_O,ARDY,dsprst,xreset,saareset,EA_SRAM,CE_SRAM,WE_SRAM,OE_SRAM);

	//input
	    /*___________________________________________________ */
		//reset
		input reset;//active low, board reset;
		
	    /*___________________________________________________ */
		//From Dsp TMSC6711
		input CE3_;//EMIF CE3 space enable
		input ARE_;//active low,asynchronous memory read strobe
		input AWE_;//active low,asynchronous memory write strobe


		//EMIF word address bits [21..16], [6..2]
		input [21:2] EA;
		
		//EMIF DATA BUS INPUT
		input [7:0] ED_I;
		
		//DATA FROM SRAM
		input [7:0] ED_SRAM;
		


	//output


	    /*___________________________________________________ */
		//TO DSP TMSC6711
		output ARDY;//EMIF async memory access ready
		
		//EMIF DATA BUS OUTPUT
		output [7:0] ED_O;
		output ED_OEN_O;

		//TO LWBRESET
		output dsprst;
		output xreset;
		output saareset;

		//TO SRAM
		output [18:0] EA_SRAM;
		output CE_SRAM;//ACTIVE LOW
		output OE_SRAM;//ACTIVE LOW FOR READ
		output WE_SRAM;//ACTIVE LOW FOR WRITE,HIGH FOR READ
	//WIRES
	    /*___________________________________________________ */
		//
	


	//Parameter
	    /*___________________________________________________ */
		//Internal register
		parameter IN_REG_ADDR = 6'b001000;//0xB0,08x,xxx
		
	    /*___________________________________________________ */
		//internal register offset [EA6..EA2]
		parameter DSP_STA_ADR = 0;// CE3: OXB0,080,000
		parameter SAA_STA_ADR = 1;// CE3: 0XB0,080,004
		parameter SAA_CNTL_ADR = 2;//CE3: 0XB0,080,008
		parameter DAU_CNTL_ADR = 3;// CE3:0XBO,080,00C
		parameter [7:0] REG_RSVD = 8'h00;

	//=================================================================================
	//internal registers
	//=================================================================================
	    /*___________________________________________________ */
		//DSP STATE register,CE3:B0,080,000 
		//0BIT:INIT_FLAG
		//1BIT:DATA_PRE
		reg [7:0] DSP_STA_REG;


	    /*___________________________________________________ */
		//DSP control register,not map in DSP address 
		//0BIT:dsprst
		reg [7:0] DSP_CNTL_REG;


	    /*___________________________________________________ */
		//SAA7113 STATE register,CE3:B0,080,004
		//0BIT:INIT_FLAG
		//1BIT:DATA_WR
		reg [7:0] SAA_STA_REG;

	    /*___________________________________________________ */
		//SAA7113 CONTROL register,CE3:B0,080,008 
		//0BIT:saareset
		reg [7:0] SAA_CNTL_REG;

	    /*___________________________________________________ */
		//DAUGHTER CARD CONTROL register,CE3:B0,080,00C 
		//0BIT:xreset
//		output [7:0] DAU_CNTL_REG;//just for test,may be delete after test
		reg [7:0] DAU_CNTL_REG;

		
		reg ED_OEN_O;
		reg [7:0] ED_O;

		//TO SRAM
		reg [18:0] EA_SRAM;//TO SRAM
		reg CE_SRAM;
		reg WE_SRAM;
		reg OE_SRAM;



	//ASSIGNING

	    /*___________________________________________________ */
		//DSP Asynchronous Memory Access ARDY Generation
		assign ARDY = (!CE3_ && (EA[21:16] == IN_REG_ADDR)) ? (!ARE_ || !AWE_) : 1'bz;//FPGA Internal register accesses are ready when ARE_ or AWE_ goes low

		assign dsprst = DSP_CNTL_REG[0];//no use
		assign xreset = DAU_CNTL_REG[0];
		assign saareset = SAA_CNTL_REG[0];
		


	//DECODE CONTROL
	    /*___________________________________________________ */
		//Internal mapped register writes
		always @( AWE_ or ARE_ or reset or CE3_ or  EA or ED_I or ED_SRAM)
			if(!reset)
				begin
					DSP_STA_REG <= #1 8'h00;
//					DSP_CNTL_REG <= #1 8'h00;
					SAA_STA_REG <= #1 8'b00000010;
					SAA_CNTL_REG <= #1 8'h00;
					DAU_CNTL_REG <= #1 8'h00;
					ED_OEN_O <= #1 1'b0;
					ED_O <= #1 8'h00;
				end
			else if (!AWE_ && !CE3_ && (EA[21:16] == IN_REG_ADDR))
				begin
					case (EA[6:2])
						DSP_STA_ADR :
							begin
								DSP_STA_REG <= #1 ED_I;
								ED_OEN_O <= #1 1'b0;
							end
						SAA_STA_ADR:
							begin
								SAA_STA_REG <= #1 ED_I;
								ED_OEN_O <= #1 1'b0;
							end
						SAA_CNTL_ADR :
							begin
								SAA_CNTL_REG <= #1 ED_I;
								ED_OEN_O <= #1 1'b0;
							end
						DAU_CNTL_ADR :
							begin
								DAU_CNTL_REG <= #1 ED_I;
								ED_OEN_O <= #1 1'b0;
							end
					endcase
				end
			else if (!ARE_ && !CE3_ && (EA[21:16] == IN_REG_ADDR))
					begin
						case (EA[6:2])
							DSP_STA_ADR :
								begin
									ED_O <= #1 DSP_STA_REG;
									ED_OEN_O <= #1 1'b1;
								end
							SAA_STA_ADR :
								begin
									ED_O <= #1 SAA_STA_REG;
									ED_OEN_O <= #1 1'b1;
								end
							SAA_CNTL_ADR :
								begin
									ED_O <= #1 SAA_CNTL_REG;
									ED_OEN_O <= #1 1'b1;
								end
							DAU_CNTL_ADR :
								begin
									ED_O <= #1 DAU_CNTL_REG;
									ED_OEN_O <= #1 1'b1;
								end
							default :
								begin
									ED_O <= #1 REG_RSVD;
									ED_OEN_O <= #1 1'b1;
								end
							endcase
					end
			else if (!ARE_ && !CE3_ && (EA[21:16] < IN_REG_ADDR ))
				begin
					CE_SRAM <= 1'b0;
					EA_SRAM <= EA[20:2];
					WE_SRAM <= #12 1'b1;
					OE_SRAM <= #12 1'b0;
					ED_O <= #20 ED_SRAM;
					ED_OEN_O <= #1 1'b1;
				end

		
endmodule