df8.vhd

基于VHDL的串行异步通信电路的设计 包括串行发送器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_unsigned.all;

entity DF8 is 
port (
      CLK_IN:  in std_logic;
      CLK_OUT: out std_logic);
      
end;

architecture main of df8 is

signal clk:std_logic:='0';
signal a: integer range 0 to 7;


begin 
   process (clk_in)
     begin
      
       if CLK_IN'event and CLK_IN='1' then

           if a=3 then
                 clk<= not clk;
                 a<=a+1;
           elsif a=7 then
                 clk<= not clk;
                 a<=0;
           else
           a<=a+1;
           end if;
             
       end if;
      
   end process;
clk_out<=clk;
end;