txmiter.vhd

基于VHDL的串行异步通信电路的设计 包括串行发送器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY TxMITER IS
PORT(
     INPUT: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
     RESET,TCLK,WR,ETBE,CS,A0: IN STD_LOGIC;
     OUTPUT,TBE: OUT STD_LOGIC;
     M:OUT STD_LOGIC;
     TIRQ,CLK,START: OUT STD_LOGIC);
     
END;

ARCHITECTURE MAIN OF TxMITER IS
SIGNAL TBE_TEMP: STD_LOGIC;
SIGNAL REG_TB: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL REG_TS: STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL COUNTER: INTEGER RANGE 0 TO 8;
SIGNAL MOV,TEMP,TxCLK: STD_LOGIC;
SIGNAL DATA:STD_LOGIC;
COMPONENT DF8 
PORT(
     clk_in:  in std_logic;
     clk_out: out std_logic
     );
END COMPONENT;

BEGIN
U1: DF8 PORT MAP(TCLK,TxCLK);
  PROCESS(TxCLK,TBE_TEMP,ETBE,MOV,REG_TB,REG_TS)
    BEGIN
     
      IF TBE_TEMP='1' AND ETBE='1' THEN
         TIRQ<='1';
      ELSE 
         TIRQ<='0';
      END IF;


      IF TxCLK'EVENT AND TxCLK='1' THEN
       IF RESET='0' THEN 
          REG_TS<="000000000";
          TBE_TEMP<='1';
          REG_TB<="00000000";
          COUNTER<=0;
          START<='0';
          MOV<='0';
          TEMP<='0';
       ELSE
 
       IF CS='0' AND (A0='0' OR WR='1')  THEN 
       
        IF TEMP='0' THEN 
           TBE_TEMP<='1';
           TEMP<='1';
           REG_TS<="000000000";
        ELSIF TEMP<='1' AND WR='0' AND TBE_TEMP='1' THEN
           REG_TB<=INPUT;
           TBE_TEMP<='0';
        ELSIF TEMP<='1' AND TBE_TEMP='0' AND MOV='0'  THEN
            REG_TS(7 DOWNTO 0)<=NOT REG_TB;
            REG_TS(8)<='1'; 
            TBE_TEMP<='1';
            COUNTER<=0;
            MOV<='1';
            START<='1';
        ELSIF MOV='1' AND COUNTER<=7 THEN
              REG_TS(1)<=REG_TS(0);
              REG_TS(2)<=REG_TS(1);
              REG_TS(3)<=REG_TS(2);
              REG_TS(4)<=REG_TS(3);
              REG_TS(5)<=REG_TS(4);
              REG_TS(6)<=REG_TS(5);
              REG_TS(7)<=REG_TS(6);
              REG_TS(8)<=REG_TS(7);
              COUNTER<=COUNTER+1;
        ELSIF COUNTER=8 THEN
              REG_TS<="000000000";
              MOV<='0';
              COUNTER<=0;
        END IF;
      END IF;
      END IF;
     END IF;

    
CLK<=TxCLK;
--T<=TEMP;
--R1<=REG_TB;
--R2<=REG_TS;
TBE<=TBE_TEMP;
M<=MOV;
OUTPUT<=NOT REG_TS(8);
  END PROCESS;
END;