asynrcv.vhd

基于VHDL的串行异步通信电路的设计 包括串行发送器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY ASYNRCV IS
PORT(
     RESET,RXC,RXD,RE,ERBF,ERXE,CS,A0: IN STD_LOGIC;
     OUTPUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
     FE,OE,PE,RBF,RIRQ: OUT STD_LOGIC);
     
END;

ARCHITECTURE MAIN OF ASYNRCV IS
SIGNAL DATA1: STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL SCLK,LDSR,LDRB,S0,RBF_TEMP,OE_TEMP,FE_TEMP,PE_TEMP,READ: STD_LOGIC;
SIGNAL DATA:STD_LOGIC_VECTOR(7 DOWNTO 0);
COMPONENT RCCTRL
PORT(
     RESET,CS,A0,RE,RXC,RXD,S0:  IN  STD_LOGIC;
     LDSR,LDRB,SCLK,FE:   OUT STD_LOGIC);
END COMPONENT;

COMPONENT RB
PORT(
     INPUT: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
     RESET,RXC,RE,LDRB:IN STD_LOGIC;
     OUTPUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;

COMPONENT RS
PORT(
     RESET,RXC,RXD:  IN STD_LOGIC; 
     SCLK: IN STD_LOGIC;
     LDSR: IN STD_LOGIC;
     S0:   OUT STD_LOGIC;
     OUTPUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;

BEGIN
u1:  RCCTRL PORT MAP(RESET,CS,A0,RE,RXC,RXD,S0,LDSR,LDRB,SCLK,FE_TEMP);
u2:  RS PORT MAP(RESET,RXC,RXD,SCLK,LDSR,S0,DATA);
u3:  RB PORT MAP(DATA,RESET,RXC,RE,LDRB,DATA1);

PROCESS(RXC,RBF_TEMP,LDRB,ERBF)
BEGIN
  IF RXC'EVENT AND RXC='1' THEN
    IF RESET='0' THEN
       PE_TEMP<='0';OE_TEMP<='0';RBF_TEMP<='0';READ<='0';



    ELSE  
    IF (ERBF='1' AND RBF_TEMP='1') OR (ERXE='1' AND (FE_TEMP='1' OR OE_TEMP='1' OR PE_TEMP='1')) THEN
       RIRQ<='1';
    ELSE RIRQ<='0';
    END IF;
    IF READ='1' AND( (RE='0' AND A0='0' ) OR RE='1') THEN
       OE_TEMP<='0'; 

       
    ELSIF RBF_TEMP='0' AND LDRB='1'  THEN RBF_TEMP<='1';
    ELSIF RBF_TEMP='1' AND RE='0'AND A0='0' THEN RBF_TEMP<='0';
    ELSIF RBF_TEMP='1' AND LDRB='1' THEN OE_TEMP<='1';
    END IF;
    IF READ='0' AND RE='0' AND A0='0' THEN
       IF (DATA(0) XOR DATA(1) XOR DATA(2) XOR DATA(3) XOR DATA(4) XOR DATA(5) XOR DATA(6) XOR DATA(7))='1' THEN
           PE_TEMP<='0';
       ELSE PE_TEMP<='1';
       END IF;
    ELSIF READ='1' AND RE='0' AND A0='0' THEN
       PE_TEMP<='0';
    ELSIF RE='1' THEN
       PE_TEMP<='0';READ<='0';
    END IF;
    IF RE='0' AND A0='1' THEN 
       READ<='1';
    END IF;
   END IF;
   END IF;
    
  

END PROCESS;





OUTPUT<=DATA1;
RBF<=RBF_TEMP;
OE<=OE_TEMP;
PE<=PE_TEMP;
FE<=FE_TEMP;
END;