rb.vhd

基于VHDL的串行异步通信电路的设计 包括串行发送器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY RB IS
PORT(
     INPUT: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
     RESET,RXC,RE,LDRB:IN STD_LOGIC;
     OUTPUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END;

ARCHITECTURE MAIN OF RB IS 

SIGNAL REG: STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN 
  
  PROCESS(LDRB,RE,REG,INPUT,RXC)
   BEGIN 
     IF RXC'EVENT AND RXC='1' THEN
      IF RESET='0' THEN
         REG<="00000000";
         OUTPUT<="00000000";
      ELSE
      IF LDRB='1' THEN
      REG<=INPUT;
      END IF;
      IF RE='0' THEN
      OUTPUT<=REG;
      END IF;
     END IF;
     END IF;
   END PROCESS;
END;