rs.vhd

基于VHDL的串行异步通信电路的设计 包括串行发送器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY RS IS
PORT(
     RESET,RXC,RXD:  IN STD_LOGIC; 
     SCLK: IN STD_LOGIC;
     LDSR: IN STD_LOGIC;
     S0:   OUT STD_LOGIC;
     OUTPUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END;

ARCHITECTURE MAIN OF RS IS
SIGNAL REG: STD_LOGIC_VECTOR(8 DOWNTO 0);
BEGIN
  
  PROCESS(LDSR,SCLK,REG(8),RXC)
    
    BEGIN
      
      IF RXC'EVENT AND RXC='1' THEN
        
         IF REG(8)='0' THEN
            OUTPUT<=REG(7 DOWNTO 0);
         END IF;
        
      END IF;
      IF SCLK'EVENT AND SCLK='1' THEN
        
        IF LDSR='1' THEN
         REG<="111111110";
         
        ELSE
         
         REG(1)<=REG(0);
         REG(2)<=REG(1);
         REG(3)<=REG(2);
         REG(4)<=REG(3);
         REG(5)<=REG(4);
         REG(6)<=REG(5);
         REG(7)<=REG(6);
         REG(8)<=REG(7);
         REG(0)<=RXD;
        END IF;


      END IF;
      


  END PROCESS;

S0<=REG(8);
END;