📄 asyncmc.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ASYNCMC IS
PORT(
DIN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CS,RD,WR,A0,TXC,RXC,RXD,RESET: IN STD_LOGIC;
STS:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
TIRQ,RIRQ,TXD,CLK: OUT STD_LOGIC);
END;
ARCHITECTURE MAIN OF ASYNCMC IS
SIGNAL REG_STATUS,INPUT,OUTPUT,DDDD: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL TEMP,TXD_TEMP,TXD3,ETBE,ERBF,ERXE,TBE,FE,OE,PE,RBF,START:STD_LOGIC;
COMPONENT TxMITER
PORT(
INPUT: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
RESET,TCLK,WR,ETBE,CS,A0: IN STD_LOGIC;
OUTPUT,TBE: OUT STD_LOGIC;
TIRQ,CLK,START: OUT STD_LOGIC);
END COMPONENT;
COMPONENT ASYNRCV
PORT(
RESET,RXC,RXD,RE,ERBF,ERXE,CS,A0: IN STD_LOGIC;
OUTPUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
FE,OE,PE,RBF,RIRQ: OUT STD_LOGIC);
END COMPONENT;
BEGIN
U1: TxMITER PORT MAP (INPUT,RESET,TXC,WR,ETBE,CS,A0,TXD3,TBE,TIRQ,CLK,START);
U2: ASYNRCV PORT MAP (RESET,RXC,TXD_TEMP,RD,ERBF,ERXE,CS,A0,OUTPUT,FE,OE,PE,RBF,RIRQ);
PROCESS(RXC,CS,A0,RD,WR)
VARIABLE STAT:STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE REG_STATUS:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
STAT:=CS&A0&RD≀
IF RXC'EVENT AND RXC='1' THEN
IF RESET='0' THEN
TEMP<='0';REG_STATUS:="00000000";TXD_TEMP<='1';DDDD<="00000000";ETBE<='0';ERBF<='0';INPUT<="00000000";ERXE<='0';
ELSE
IF TEMP='0' THEN
REG_STATUS:="00000010";
TEMP<='1';TXD_TEMP<='1';
ELSIF START='1' THEN TXD_TEMP<=TXD3;
END IF;
REG_STATUS:='0'&'0'&'0'&FE&OE&PE&TBE&RBF;
CASE STAT IS
WHEN "0001"=>DDDD<=OUTPUT;
WHEN "0010"=>INPUT<=DIN;
WHEN "0101"=>
DDDD<=REG_STATUS;
WHEN "0110"=>
ETBE<=DIN(1);
ERBF<=DIN(0);
ERXE<=DIN(2);
WHEN OTHERS=>DDDD<=DDDD;
END CASE;
END IF;
END IF;
END PROCESS;
STS<='0'&'0'&'0'&FE&OE&PE&TBE&RBF;
TXD<=TXD_TEMP;
DOUT<="ZZZZZZZZ" WHEN CS='1' ELSE DDDD;
END;
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