controller.vhd

来自「非整数分频器 分频系数为无限不循环小数 vhdl」· VHDL 代码 · 共 33 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity controller is
	port(clk : in std_logic;
         count_ctrl:in std_logic;
		 control_signal:out std_logic);
end;

architecture main of controller is
signal count: integer range 0 to 32;
signal q,p: std_logic;
begin

process(clk,count_ctrl)
begin
 if falling_edge(clk) then
      if count_ctrl='1' then count<=count+1;
           else if count=32 then count<=0;
			    end if;     
	  end if;
      if (count=1 or count=4 or count=6 or count=9 or count=11 or count=14 or count=16 or count=19 or count=21 or count=24 or count=26 or count=29 or count=31) then
		    p<='1';
	    else
		    p<='0';
	  end if;
 end if;
control_signal<=p;
end process;
end;