mux8_4.vhd

FPGA-based_oscilloscope,VHDL写的实现 示波器的程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux8_4 is
    Port ( clock : in std_logic;
           read : in std_logic;
           y0,y1,y3 : out std_logic;
           sel : in std_logic
          -- den : in std_logic
			 );
end mux8_4;

architecture Behavioral of mux8_4 is

begin
	process(sel,clock,read)
	begin
if (sel='1')then
y0<=read;
y1<='0';
y3<='1';
else
y0<=clock;
y1<='1';
--y3<=not clock;
y3<=clock;
--y3<='0';
end if;
	end process;
end Behavioral;