malvino.vhd

FPGA-based_oscilloscope,VHDL写的实现 示波器的程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity conter is
    Port ( clk : in std_logic;
	 			en: in std_logic;
           cnt : out std_logic;
			  address1:out std_logic_vector(7 downto 0)
			  );
end conter;

architecture Behavioral of conter is
signal cont : std_logic_vector(30 downto 0):=(others=>'1');
begin
process(clk)
begin
if(en='1' or cont(8)='1')then
if(clk'event and clk='1')then

cont<=cont+1;
end if;
else
cont<=(others=>'0');
end if;
end process;
cnt<=cont(8);
address1<=cont(7 downto 0);



end Behavioral;