conve.vhd

FPGA-based_oscilloscope,VHDL写的实现 示波器的程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity convert is
    Port ( 
	 		  enable : in std_logic;
           clk : in std_logic;
           data1 : in std_logic_vector(7 downto 0);
           read : out std_logic;
           data2 : inout std_logic_vector(7 downto 0);
           address : out std_logic_vector(14 downto 0);
			  oeb: out std_logic; 
			  web: out std_logic;
			  clr: out std_logic;
			  start : in std_logic;
           done : out std_logic);
end convert;

architecture behavioral of convert is

signal temp: std_logic_vector(15 downto 0);
--signal pixel : std_logic_vector(3 downto 0);
signal dada,dada2 : std_logic_vector(7 downto 0);
signal timer : std_logic_vector(8 downto 0);
--signal x: std_logic_vector(1 downto 0);
--signal y: std_logic_vector(4 downto 0);
--signal z: std_logic_vector(7 downto 0);


begin

process(start,clk)

begin
if(enable='1')then

	--clear memory--
  if(start='1' )then
  	if(clk'event and clk='1')then
	read<='0';
	web <= '0';
	clr <='0';
	oeb <= '1';
	timer <= "000000000";
	address <=temp(15 downto 1);
	temp <= temp + 1;
--	for add in 0 to 4095 loop
--		address <="111" & CONV_STD_LOGIC_VECTOR(add,12) ;
--	data2 <= "11111111";
--	end loop;
-------------------------------------------

if (temp<32768 and temp>32640 ) then
data2<="00000000";
else
data2 <= "11111111";
end if;
if (temp(5 downto 0)=32)then
data2<="00111111";
	if(temp<32768 and temp>32640)then
		data2<="00000000";
	end if;
		
end if;

--------------------------------------
if(temp(15 downto 1)=32767)then
			clr<='1';
			temp<="0000000000000000";
		end if;
--		clr<=cl;
	end if;
  
  elsif(clk'event and clk='1')then
---------------------------
--	clr<='0';--dont forget to change this sentence active
--	read <= '0';	---send low for read
--	if(pixel > 7) then
--		pixel <= "0000";	---after 4 pixels sent pixreg is updated
--		pixreg <= "11000000";
--	elsif (pixel = 0)then	--- set pixreg at the start of the program
--		pixreg <= "11000000";
--	end if;
--	read <= '1';
   read <= clk;	--send read pulse
	dada <= data1;--get data from data memory
--	dada<="01010101";
	address <= ("011111101"-dada(5 downto 0)) & timer(7 downto 2); 	--calculate address the original was "111111111"-----
	web <= '1';
	oeb <= '0';
	dada2 <= data2;
	
	web <= '0';
	oeb <= '1';
--	read<='0';

--	data2 <=dada2 or  pixreg;	--- mask the pixreg on dada2
	
--	pixreg <= "00" & pixreg(7 downto 2); --- shift pixreg
	
--	pixel <= pixel + 2;
elsif(clk'event and clk='0')then

	if(timer(1 downto 0) = "00")then
		data2<=dada2(7 downto 2) & "10";
		
	elsif(timer(1 downto 0) = "01")then
		data2<=dada2( 7 downto 4) & "10" & dada2(1 downto 0);
	elsif(timer(1 downto 0) = "10")then
		data2<=dada2(7 downto 6) & "10"& dada2(3 downto 0);

	elsif(timer(1 downto 0) = "11")then
		data2<= "10" & dada2(5 downto 0) ;

	end if;
	timer <= timer + 1;
	if(timer = 255)then	---check timer to end the program
		clr  <= '0';
	
		done <= '1';
		done <= '1';
		done <= '1';
		done <= '0';
	end if;
end if;
end if;
if(enable='0')then
web<='1';
oeb<='0';
data2<="ZZZZZZZZ";
dada2<=data2;
	read<='0';
end if;
end process;

end behavioral;