batmouse.vhf

FPGA-based_oscilloscope,VHDL写的实现 示波器的程序

-- Vhdl model created from schematic batmouse.sch - Mon Jun 21 22:49:06 2004

LIBRARY ieee;
LIBRARY UNISIM;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE UNISIM.Vcomponents.ALL;

ENTITY batmouse IS
   PORT ( clk	:	IN	STD_LOGIC; 
          clockdiv	:	IN	STD_LOGIC; 
          data1	:	IN	STD_LOGIC_VECTOR (7 DOWNTO 0); 
          RGB	:	OUT	STD_LOGIC_VECTOR (5 DOWNTO 0); 
          add1	:	OUT	STD_LOGIC_VECTOR (7 DOWNTO 0); 
          add2	:	OUT	STD_LOGIC_VECTOR (14 DOWNTO 0); 
          hsync	:	OUT	STD_LOGIC; 
          oeb	:	OUT	STD_LOGIC; 
          oeb1	:	OUT	STD_LOGIC; 
          q9	:	OUT	STD_LOGIC; 
          read	:	OUT	STD_LOGIC; 
          vsync	:	OUT	STD_LOGIC; 
          web	:	OUT	STD_LOGIC; 
          web1	:	OUT	STD_LOGIC; 
          data2	:	INOUT	STD_LOGIC_VECTOR (7 DOWNTO 0));

end batmouse;

ARCHITECTURE SCHEMATIC OF batmouse IS
   SIGNAL XLXN_13	:	STD_LOGIC;
   SIGNAL XLXN_5	:	STD_LOGIC;
   SIGNAL q9_DUMMY	:	STD_LOGIC;
   SIGNAL read_DUMMY	:	STD_LOGIC;

   ATTRIBUTE fpga_dont_touch : STRING ;

   COMPONENT conter
      PORT ( clk	:	IN	STD_LOGIC; 
             en	:	IN	STD_LOGIC; 
             cnt	:	OUT	STD_LOGIC; 
             address1	:	OUT	STD_LOGIC_VECTOR (7 DOWNTO 0));
   END COMPONENT;

   COMPONENT mux8_4
      PORT ( clock	:	IN	STD_LOGIC; 
             read	:	IN	STD_LOGIC; 
             sel	:	IN	STD_LOGIC; 
             y0	:	OUT	STD_LOGIC; 
             y1	:	OUT	STD_LOGIC; 
             y3	:	OUT	STD_LOGIC);
   END COMPONENT;

   COMPONENT samkmorsy
      PORT ( data1	:	IN	STD_LOGIC_VECTOR (7 DOWNTO 0); 
             vclk	:	IN	STD_LOGIC; 
             clock	:	IN	STD_LOGIC; 
             Q9	:	IN	STD_LOGIC; 
             data2	:	INOUT	STD_LOGIC_VECTOR (7 DOWNTO 0); 
             oeb	:	OUT	STD_LOGIC; 
             add2	:	OUT	STD_LOGIC_VECTOR (14 DOWNTO 0); 
             vsync	:	OUT	STD_LOGIC; 
             RGB	:	OUT	STD_LOGIC_VECTOR (5 DOWNTO 0); 
             web	:	OUT	STD_LOGIC; 
             hsync	:	OUT	STD_LOGIC; 
             reset	:	OUT	STD_LOGIC; 
             sel	:	OUT	STD_LOGIC; 
             read	:	OUT	STD_LOGIC; 
             ena	:	OUT	STD_LOGIC; 
             red	:	OUT	STD_LOGIC);
   END COMPONENT;

BEGIN
   q9 <= q9_DUMMY;
   read <= read_DUMMY;

   XLXI_4 : conter
      PORT MAP (clk=>XLXN_13, en=>XLXN_5, cnt=>q9_DUMMY, address1(7)=>add1(7),
      address1(6)=>add1(6), address1(5)=>add1(5), address1(4)=>add1(4),
      address1(3)=>add1(3), address1(2)=>add1(2), address1(1)=>add1(1),
      address1(0)=>add1(0));

   XLXI_3 : mux8_4
      PORT MAP (clock=>clockdiv, read=>read_DUMMY, sel=>q9_DUMMY, y0=>XLXN_13,
      y1=>oeb1, y3=>web1);

   XLXI_2 : samkmorsy
      PORT MAP (data1(7)=>data1(7), data1(6)=>data1(6), data1(5)=>data1(5),
      data1(4)=>data1(4), data1(3)=>data1(3), data1(2)=>data1(2),
      data1(1)=>data1(1), data1(0)=>data1(0), vclk=>clk, clock=>clk,
      Q9=>q9_DUMMY, data2(7)=>data2(7), data2(6)=>data2(6), data2(5)=>data2(5),
      data2(4)=>data2(4), data2(3)=>data2(3), data2(2)=>data2(2),
      data2(1)=>data2(1), data2(0)=>data2(0), oeb=>oeb, add2(14)=>add2(14),
      add2(13)=>add2(13), add2(12)=>add2(12), add2(11)=>add2(11),
      add2(10)=>add2(10), add2(9)=>add2(9), add2(8)=>add2(8), add2(7)=>add2(7),
      add2(6)=>add2(6), add2(5)=>add2(5), add2(4)=>add2(4), add2(3)=>add2(3),
      add2(2)=>add2(2), add2(1)=>add2(1), add2(0)=>add2(0), vsync=>vsync,
      RGB(5)=>RGB(5), RGB(4)=>RGB(4), RGB(3)=>RGB(3), RGB(2)=>RGB(2),
      RGB(1)=>RGB(1), RGB(0)=>RGB(0), web=>web, hsync=>hsync, reset=>open,
      sel=>open, read=>open, ena=>XLXN_5, red=>read_DUMMY);

END SCHEMATIC;