📄 i2c.fit.rpt
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+----------------------------+--------------------+
+-----------------------------------------------------------------------------+
; LAB External Interconnect ;
+-----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 22.50) ; Number of LABs (Total = 8) ;
+-----------------------------------------------+-----------------------------+
; 0 - 2 ; 0 ;
; 3 - 5 ; 0 ;
; 6 - 8 ; 0 ;
; 9 - 11 ; 0 ;
; 12 - 14 ; 1 ;
; 15 - 17 ; 1 ;
; 18 - 20 ; 0 ;
; 21 - 23 ; 3 ;
; 24 - 26 ; 2 ;
; 27 - 29 ; 0 ;
; 30 - 32 ; 0 ;
; 33 - 35 ; 1 ;
+-----------------------------------------------+-----------------------------+
+-----------------------------------------------------------------------+
; LAB Macrocells ;
+-----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 15.13) ; Number of LABs (Total = 8) ;
+-----------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 1 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 1 ;
; 16 ; 6 ;
+-----------------------------------------+-----------------------------+
+---------------------------------------------------------+
; Parallel Expander ;
+--------------------------+------------------------------+
; Parallel Expander Length ; Number of Parallel Expanders ;
+--------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 17 ;
; 2 ; 7 ;
; 3 ; 1 ;
+--------------------------+------------------------------+
+-------------------------------------------------------------------------------+
; Shareable Expander ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders (Average = 3.38) ; Number of LABs (Total = 6) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 2 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 3 ;
; 4 ; 1 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 1 ;
+-------------------------------------------------+-----------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC16 ; clk, rst, cnt_delay[9], cnt_delay[8], cnt_delay[7], cnt_delay[6], cnt_delay[5], cnt_delay[4], cnt_delay[3], cnt_delay[2], cnt_delay[1], cnt_delay[0], cnt_delay[10], start_delaycnt, main_state~608, cnt_delay[18], cnt_delay[19], cnt_delay[17], cnt_delay[16], cnt_delay[15], cnt_delay[14], cnt_delay[11], cnt_delay[13], cnt_delay[12] ; cnt_delay[19], start_delaycnt, cnt_delay[0], cnt_delay[10], cnt_delay[11], cnt_delay[12], cnt_delay[13], cnt_delay[14], cnt_delay[15], cnt_delay[16], cnt_delay[17], cnt_delay[18], main_state~65, main_state~608, cnt_delay[8] ;
; A ; LC4 ; clk, rst, cnt_delay[10], cnt_delay[9], cnt_delay[8], cnt_delay[7], cnt_delay[6], cnt_delay[5], cnt_delay[4], cnt_delay[3], cnt_delay[2], cnt_delay[1], cnt_delay[0], cnt_delay[11], start_delaycnt ; cnt_delay[19], start_delaycnt, cnt_delay[0], cnt_delay[11], cnt_delay[12], cnt_delay[13], cnt_delay[14], cnt_delay[15], cnt_delay[16], cnt_delay[17], cnt_delay[18], main_state~65, main_state~608, cnt_delay[8], cnt_delay[10] ;
; A ; LC9 ; clk, rst, cnt_delay[11], cnt_delay[10], cnt_delay[9], cnt_delay[8], cnt_delay[7], cnt_delay[6], cnt_delay[5], cnt_delay[4], cnt_delay[3], cnt_delay[2], cnt_delay[1], cnt_delay[0], cnt_delay[12], start_delaycnt, main_state~608, cnt_delay[18], cnt_delay[19], cnt_delay[17], cnt_delay[16], cnt_delay[15], cnt_delay[14], cnt_delay[13] ; cnt_delay[19], start_delaycnt, cnt_delay[0], cnt_delay[12], cnt_delay[13], cnt_delay[14], cnt_delay[15], cnt_delay[16], cnt_delay[17], cnt_delay[18], main_state~65, main_state~608, cnt_delay[8], cnt_delay[10] ;
; A ; LC5 ; clk, rst, cnt_delay[7], cnt_delay[6], cnt_delay[5], cnt_delay[4], cnt_delay[3], cnt_delay[2], cnt_delay[1], cnt_delay[0], cnt_delay[8], start_delaycnt, main_state~608, cnt_delay[18], cnt_delay[10], cnt_delay[19], cnt_delay[17], cnt_delay[16], cnt_delay[15], cnt_delay[14], cnt_delay[11], cnt_delay[9], cnt_delay[13], cnt_delay[12] ; cnt_delay[19], start_delaycnt, cnt_delay[0], cnt_delay[8], cnt_delay[9], cnt_delay[10], cnt_delay[11], cnt_delay[12], cnt_delay[13], cnt_delay[14], cnt_delay[15], cnt_delay[16], cnt_delay[17], cnt_delay[18], main_state~65, main_state~608 ;
; A ; LC11 ; clk, rst, cnt_delay[12], cnt_delay[11], cnt_delay[10], cnt_delay[9], cnt_delay[8], cnt_delay[7], cnt_delay[6], cnt_delay[5], cnt_delay[4], cnt_delay[3], cnt_delay[2], cnt_delay[1], cnt_delay[0], cnt_delay[13], start_delaycnt, main_state~608, cnt_delay[18], cnt_delay[19], cnt_delay[17], cnt_delay[16], cnt_delay[15], cnt_delay[14] ; cnt_delay[19], start_delaycnt, cnt_delay[0], cnt_delay[13], cnt_delay[14], cnt_delay[15], cnt_delay[16], cnt_delay[17], cnt_delay[18], main_state~65, main_state~608, cnt_delay[8], cnt_delay[10], cnt_delay[12] ;
; A ; LC15 ; clk, rst, cnt_delay[13], cnt_delay[12], cnt_delay[11], cnt_delay[10], cnt_delay[9], cnt_delay[8], cnt_delay[7], cnt_delay[6], cnt_delay[5], cnt_delay[4], cnt_delay[3], cnt_delay[2], cnt_delay[1], cnt_delay[0], cnt_delay[14], start_delaycnt ; cnt_delay[19], start_delaycnt, cnt_delay[0], cnt_delay[14], cnt_delay[15], cnt_delay[16], cnt_delay[17], cnt_delay[18], main_state~65, main_state~608, cnt_delay[8], cnt_delay[10], cnt_delay[12], cnt_delay[13] ;
; A ; LC14 ; clk, rst, cnt_delay[14], cnt_delay[13], cnt_delay[12], cnt_delay[11], cnt_delay[10], cnt_delay[9], cnt_delay[8], cnt_delay[7], cnt_delay[6], cnt_delay[5], cnt_delay[4], cnt_delay[3], cnt_delay[2], cnt_delay[1], cnt_delay[0], cnt_delay[15], start_delaycnt ; cnt_delay[19], start_delaycnt, cnt_delay[0], cnt_delay[15], cnt_delay[16], cnt_delay[17], cnt_delay[18], main_state~65, main_state~608, cnt_delay[8], cnt_delay[10], cnt_delay[12], cnt_delay[13] ;
; A ; LC13 ; clk, rst, cnt_delay[15], cnt_delay[14], cnt_delay[13], cnt_delay[12], cnt_delay[10], cnt_delay[11], cnt_delay[8], cnt_delay[9], cnt_delay[7], cnt_delay[6], cnt_delay[5], cnt_delay[4], cnt_delay[3], cnt_delay[2], cnt_delay[1], cnt_delay[0], start_delaycnt ; cnt_delay[19], start_delaycnt, cnt_delay[0], cnt_delay[17], cnt_delay[18], main_state~65, main_state~608, cnt_delay[8], cnt_delay[10], cnt_delay[12], cnt_delay[13] ;
; A ; LC10 ; clk, rst, cnt_delay[16], cnt_delay[15], cnt_delay[14], cnt_delay[13], cnt_delay[12], cnt_delay[10], cnt_delay[11], cnt_delay[8], cnt_delay[9], cnt_delay[7], cnt_delay[6], cnt_delay[5], cnt_delay[4], cnt_delay[3], cnt_delay[2], cnt_delay[1], cnt_delay[0], cnt_delay[17], start_delaycnt ; cnt_delay[19], start_delaycnt, cnt_delay[0], cnt_delay[17], cnt_delay[18], main_state~65, main_state~608, cnt_delay[8], cnt_delay[10], cnt_delay[12], cnt_delay[13] ;
; A ; LC6 ; clk, rst, cnt_delay[17], cnt_delay[16], cnt_delay[15], cnt_delay[14], cnt_delay[13], cnt_delay[12], cnt_delay[10], cnt_delay[11], cnt_delay[8], cnt_delay[9], cnt_delay[7], cnt_delay[6], cnt_delay[5], cnt_delay[4], cnt_delay[3], cnt_delay[2], cnt_delay[1], cnt_delay[0], cnt_delay[18], start_delaycnt, main_state~608, cnt_delay[19] ; cnt_delay[19], start_delaycnt, cnt_delay[0], cnt_delay[18], main_state~65, main_state~608, cnt_delay[8], cnt_delay[10], cnt_delay[12], cnt_delay[13] ;
; A ; LC3 ; clk, rst, main_state~66, cnt_delay[18], cnt_delay[10], cnt_delay[8], cnt_delay[19], cnt_delay[17], cnt_delay[16], cnt_delay[15], cnt_delay[14], cnt_delay[11], cnt_delay[9], cnt_delay[7], cnt_delay[6], cnt_delay[5], cnt_delay[4], cnt_delay[3], cnt_delay[2], cnt_delay[1], cnt_delay[0], cnt_delay[13], cnt_delay[12], rd_input, wr_input, inner_state~112, main_state~65, main_state~601, i2c_state~51, i2c_state~52, main_state~602, main_state~600 ; Select~6428, inner_state~113, inner_state~115, inner_state~4136, inner_state~4138, inner_state~114, inner_state~112, i2c_state~52, i2c_state~51, i2c_state~50, main_state~65, sda_buf, readData_reg[0], readData_reg[1], main_state~66, readData_reg[2], readData_reg[3], readData_reg[4], readData_reg[5], readData_reg[6], readData_reg[7], Select~6482, Select~6488, Select~6494, inner_state~4153, inner_state~4159, inner_state~4165, inner_state~4167, inner_state~4173, inner_state~4175, inner_state~4181, sda~15, readData_reg[0]~191, main_state~617, readData_reg[1]~195, readData_reg[2]~199, readData_reg[3]~203, readData_reg[4]~207, readData_reg[5]~211, readData_reg[6]~215 ;
; A ; LC2 ; clk, rst, main_state~617, main_state~65, main_state~66, i2c_state~51, i2c_state~50, i2c_state~52, inner_state~112, inner_state~114, phase3, rd_input, wr_input, main_state~608, main_state~609, sda_buf, phase1, inner_state~113 ; writeData_reg[3], writeData_reg[1], writeData_reg[2], writeData_reg[0], start_delaycnt, inner_state~114, inner_state~112, i2c_state~52, i2c_state~51, i2c_state~50, main_state~65, main_state~66, scl~reg0, Select~6482, inner_state~4153, inner_state~4165, inner_state~4181, main_state~617, sda_buf ;
; A ; LC1 ; main_state~65, sda_buf, phase1, inner_state~112, inner_state~113, main_state~66, inner_state~114, phase3, i2c_state~51, i2c_state~50 ; main_state~66 ;
; A ; LC12 ; clk, rst, cnt_delay[18], cnt_delay[17], cnt_delay[16], cnt_delay[15], cnt_delay[14], cnt_delay[13], cnt_delay[12], cnt_delay[10], cnt_delay[11], cnt_delay[8], cnt_delay[9], cnt_delay[7], cnt_delay[6], cnt_delay[5], cnt_delay[4], cnt_delay[3], cnt_delay[2], cnt_delay[1], cnt_delay[0], cnt_delay[19], start_delaycnt, main_state~608 ; cnt_delay[19], start_delaycnt, cnt_delay[0], main_state~65, main_state~608, cnt_delay[8], cnt_delay[10], cnt_delay[12], cnt_delay[13], cnt_delay[18] ;
; A ; LC7 ; clk, rst, rd_input, cnt_delay[18], cnt_delay[10], cnt_delay[8], cnt_delay[19], cnt_delay[17], cnt_delay[16], cnt_delay[15], cnt_delay[14], cnt_delay[11], cnt_delay[9], cnt_delay[7], cnt_delay[6], cnt_delay[5], cnt_delay[4], cnt_delay[3], cnt_delay[2], cnt_delay[1], cnt_delay[0], cnt_delay[13], cnt_delay[12], start_delaycnt, wr_input, main_state~66 ; cnt_delay[19], start_delaycnt, cnt_delay[0], cnt_delay[1], cnt_delay[2], cnt_delay[3], cnt_delay[4], cnt_delay[5], cnt_delay[6], cnt_delay[7], cnt_delay[8], cnt_delay[9], cnt_delay[10], cnt_delay[11], cnt_delay[12], cnt_delay[13], cnt_delay[14], cnt_delay[15], cnt_delay[16], cnt_delay[17], cnt_delay[18] ;
; A ; LC8 ; clk, rst, cnt_delay[18], cnt_delay[10], cnt_delay[8], cnt_delay[19], cnt_delay[17], cnt_delay[16], cnt_delay[15], cnt_delay[14], cnt_delay[11], cnt_delay[9], cnt_delay[7], cnt_delay[6], cnt_delay[5], cnt_delay[4], cnt_delay[3], cnt_delay[2], cnt_delay[1], cnt_delay[13], cnt_delay[12], cnt_delay[0], start_delaycnt ; cnt_delay[19], start_delaycnt, cnt_delay[0], cnt_delay[1], cnt_delay[2], cnt_delay[3], cnt_delay[4], cnt_delay[5], cnt_delay[6], cnt_delay[7], cnt_delay[8], cnt_delay[9], cnt_delay[10], cnt_delay[11], cnt_delay[12], cnt_delay[13], cnt_delay[14], cnt_delay[15], cnt_delay[16], cnt_delay[17], cnt_delay[18], main_state~65, main_state~608 ;
; B ; LC20 ; clk, rst, data_in[1], main_state~66 ; reduce_or~2464, reduce_or~2467, reduce_or~2468, reduce_or~2472, reduce_or~2482, reduce_or~2488, reduce_or~2502, reduce_or~2509, Select~6534, reduce_or~2516, reduce_or~2520, reduce_or~2526, reduce_or~2531, reduce_or~2536 ;
; B ; LC32 ; clk, rst, data_in[2], main_state~66 ; Select~6462, reduce_or~2464, reduce_or~2467, reduce_or~2468, reduce_or~2472, reduce_or~2488, reduce_or~2502, reduce_or~2509, reduce_or~2516, reduce_or~2520, reduce_or~2526, reduce_or~2531, reduce_or~2536 ⌨️ 快捷键说明
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