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📄 i2c.tan.qmsg

📁 verilog 编写的I2c协议程序
💻 QMSG
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{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clk register main_state~66 register writeData_reg\[3\] 5.0 ns " "Info: Minimum slack time is 5.0 ns for clock \"clk\" between source register \"main_state~66\" and destination register \"writeData_reg\[3\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Shortest register register " "Info: + Shortest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns main_state~66 1 REG LC2 27 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2; Fanout = 27; REG Node = 'main_state~66'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "" { main_state~66 } "NODE_NAME" } "" } } { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 34 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns writeData_reg\[3\] 2 REG LC39 19 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC39; Fanout = 19; REG Node = 'writeData_reg\[3\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "8.000 ns" { main_state~66 writeData_reg[3] } "NODE_NAME" } "" } } { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 39 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.000 ns 75.00 % " "Info: Total cell delay = 6.000 ns ( 75.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 25.00 % " "Info: Total interconnect delay = 2.000 ns ( 25.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "8.000 ns" { main_state~66 writeData_reg[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.000 ns" { main_state~66 writeData_reg[3] } { 0.0ns 2.0ns } { 0.0ns 6.0ns } } }  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "3.000 ns - Smallest register register " "Info: - Smallest register to register requirement is 3.000 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 22.222 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk\" is 22.222 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 22.222 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clk\" is 22.222 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 70 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 70; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "" { clk } "NODE_NAME" } "" } } { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns writeData_reg\[3\] 2 REG LC39 19 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC39; Fanout = 19; REG Node = 'writeData_reg\[3\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "0.000 ns" { clk writeData_reg[3] } "NODE_NAME" } "" } } { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 39 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "3.000 ns" { clk writeData_reg[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out writeData_reg[3] } { 0.0ns 0.0ns 0.0ns } { 0.0ns 3.0ns 0.0ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 70 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 70; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "" { clk } "NODE_NAME" } "" } } { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns main_state~66 2 REG LC2 27 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC2; Fanout = 27; REG Node = 'main_state~66'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "0.000 ns" { clk main_state~66 } "NODE_NAME" } "" } } { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 34 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "3.000 ns" { clk main_state~66 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out main_state~66 } { 0.0ns 0.0ns 0.0ns } { 0.0ns 3.0ns 0.0ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "3.000 ns" { clk writeData_reg[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out writeData_reg[3] } { 0.0ns 0.0ns 0.0ns } { 0.0ns 3.0ns 0.0ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "3.000 ns" { clk main_state~66 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out main_state~66 } { 0.0ns 0.0ns 0.0ns } { 0.0ns 3.0ns 0.0ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns - " "Info: - Micro clock to output delay of source is 1.000 ns" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 34 -1 0 } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 39 -1 0 } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "3.000 ns" { clk writeData_reg[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out writeData_reg[3] } { 0.0ns 0.0ns 0.0ns } { 0.0ns 3.0ns 0.0ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "3.000 ns" { clk main_state~66 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out main_state~66 } { 0.0ns 0.0ns 0.0ns } { 0.0ns 3.0ns 0.0ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "8.000 ns" { main_state~66 writeData_reg[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.000 ns" { main_state~66 writeData_reg[3] } { 0.0ns 2.0ns } { 0.0ns 6.0ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "3.000 ns" { clk writeData_reg[3] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out writeData_reg[3] } { 0.0ns 0.0ns 0.0ns } { 0.0ns 3.0ns 0.0ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "3.000 ns" { clk main_state~66 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out main_state~66 } { 0.0ns 0.0ns 0.0ns } { 0.0ns 3.0ns 0.0ns } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "sda_buf sda clk 20.000 ns register " "Info: tsu for register \"sda_buf\" (data pin = \"sda\", clock pin = \"clk\") is 20.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "19.000 ns + Longest pin register " "Info: + Longest pin to register delay is 19.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sda 1 PIN PIN_29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_29; Fanout = 1; PIN Node = 'sda'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "" { sda } "NODE_NAME" } "" } } { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns sda~1 2 COMB IO38 20 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = IO38; Fanout = 20; COMB Node = 'sda~1'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "2.000 ns" { sda sda~1 } "NODE_NAME" } "" } } { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 11.000 ns Select~6438 3 COMB LC45 1 " "Info: 3: + IC(2.000 ns) + CELL(7.000 ns) = 11.000 ns; Loc. = LC45; Fanout = 1; COMB Node = 'Select~6438'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "9.000 ns" { sda~1 Select~6438 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 19.000 ns sda_buf 4 REG LC38 46 " "Info: 4: + IC(2.000 ns) + CELL(6.000 ns) = 19.000 ns; Loc. = LC38; Fanout = 46; REG Node = 'sda_buf'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "8.000 ns" { Select~6438 sda_buf } "NODE_NAME" } "" } } { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 29 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "15.000 ns 78.95 % " "Info: Total cell delay = 15.000 ns ( 78.95 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 21.05 % " "Info: Total interconnect delay = 4.000 ns ( 21.05 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "19.000 ns" { sda sda~1 Select~6438 sda_buf } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "19.000 ns" { sda sda~1 Select~6438 sda_buf } { 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 2.000ns 7.000ns 6.000ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 29 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 70 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 70; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "" { clk } "NODE_NAME" } "" } } { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns sda_buf 2 REG LC38 46 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC38; Fanout = 46; REG Node = 'sda_buf'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "0.000 ns" { clk sda_buf } "NODE_NAME" } "" } } { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 29 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "3.000 ns" { clk sda_buf } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out sda_buf } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "19.000 ns" { sda sda~1 Select~6438 sda_buf } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "19.000 ns" { sda sda~1 Select~6438 sda_buf } { 0.000ns 0.000ns 2.000ns 2.000ns } { 0.000ns 2.000ns 7.000ns 6.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "3.000 ns" { clk sda_buf } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out sda_buf } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk seg_data\[1\] en\[0\]~reg0 28.000 ns register " "Info: tco from clock \"clk\" to destination pin \"seg_data\[1\]\" through register \"en\[0\]~reg0\" is 28.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 70 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 70; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "" { clk } "NODE_NAME" } "" } } { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns en\[0\]~reg0 2 REG LC118 62 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC118; Fanout = 62; REG Node = 'en\[0\]~reg0'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "0.000 ns" { clk en[0]~reg0 } "NODE_NAME" } "" } } { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 698 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "3.000 ns" { clk en[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out en[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 698 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "24.000 ns + Longest register pin " "Info: + Longest register to pin delay is 24.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns en\[0\]~reg0 1 REG LC118 62 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC118; Fanout = 62; REG Node = 'en\[0\]~reg0'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "" { en[0]~reg0 } "NODE_NAME" } "" } } { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 698 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns reduce_or~2546 2 COMB LC106 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC106; Fanout = 1; COMB Node = 'reduce_or~2546'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "8.000 ns" { en[0]~reg0 reduce_or~2546 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 9.000 ns reduce_or~2516 3 COMB LC107 1 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC107; Fanout = 1; COMB Node = 'reduce_or~2516'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "1.000 ns" { reduce_or~2546 reduce_or~2516 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 11.000 ns reduce_or~2464 4 COMB LC108 1 " "Info: 4: + IC(0.000 ns) + CELL(2.000 ns) = 11.000 ns; Loc. = LC108; Fanout = 1; COMB Node = 'reduce_or~2464'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "2.000 ns" { reduce_or~2516 reduce_or~2464 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 20.000 ns reduce_or~2547 5 COMB LC99 1 " "Info: 5: + IC(2.000 ns) + CELL(7.000 ns) = 20.000 ns; Loc. = LC99; Fanout = 1; COMB Node = 'reduce_or~2547'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "9.000 ns" { reduce_or~2464 reduce_or~2547 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 24.000 ns seg_data\[1\] 6 PIN PIN_64 0 " "Info: 6: + IC(0.000 ns) + CELL(4.000 ns) = 24.000 ns; Loc. = PIN_64; Fanout = 0; PIN Node = 'seg_data\[1\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "4.000 ns" { reduce_or~2547 seg_data[1] } "NODE_NAME" } "" } } { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "20.000 ns 83.33 % " "Info: Total cell delay = 20.000 ns ( 83.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 16.67 % " "Info: Total interconnect delay = 4.000 ns ( 16.67 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "24.000 ns" { en[0]~reg0 reduce_or~2546 reduce_or~2516 reduce_or~2464 reduce_or~2547 seg_data[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "24.000 ns" { en[0]~reg0 reduce_or~2546 reduce_or~2516 reduce_or~2464 reduce_or~2547 seg_data[1] } { 0.000ns 2.000ns 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns 2.000ns 7.000ns 4.000ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "3.000 ns" { clk en[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out en[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "24.000 ns" { en[0]~reg0 reduce_or~2546 reduce_or~2516 reduce_or~2464 reduce_or~2547 seg_data[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "24.000 ns" { en[0]~reg0 reduce_or~2546 reduce_or~2516 reduce_or~2464 reduce_or~2547 seg_data[1] } { 0.000ns 2.000ns 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 6.000ns 1.000ns 2.000ns 7.000ns 4.000ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "writeData_reg\[0\] data_in\[0\] clk -3.000 ns register " "Info: th for register \"writeData_reg\[0\]\" (data pin = \"data_in\[0\]\", clock pin = \"clk\") is -3.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 70 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 70; CLK Node = 'clk'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "" { clk } "NODE_NAME" } "" } } { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns writeData_reg\[0\] 2 REG LC21 20 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC21; Fanout = 20; REG Node = 'writeData_reg\[0\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "0.000 ns" { clk writeData_reg[0] } "NODE_NAME" } "" } } { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 39 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "3.000 ns" { clk writeData_reg[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out writeData_reg[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 39 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.000 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns data_in\[0\] 1 PIN PIN_24 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_24; Fanout = 1; PIN Node = 'data_in\[0\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "" { data_in[0] } "NODE_NAME" } "" } } { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns writeData_reg\[0\] 2 REG LC21 20 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC21; Fanout = 20; REG Node = 'writeData_reg\[0\]'" {  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "8.000 ns" { data_in[0] writeData_reg[0] } "NODE_NAME" } "" } } { "i2c.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/i2c.v" 39 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "10.000 ns" { data_in[0] writeData_reg[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { data_in[0] data_in[0]~out writeData_reg[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0}  } { { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "3.000 ns" { clk writeData_reg[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.000 ns" { clk clk~out writeData_reg[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 3.000ns 0.000ns } } } { "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" "" { Report "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c_cmp.qrpt" Compiler "i2c" "UNKNOWN" "V1" "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/db/i2c.quartus_db" { Floorplan "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/接口实验/i2c总线/" "" "10.000 ns" { data_in[0] writeData_reg[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "10.000 ns" { data_in[0] data_in[0]~out writeData_reg[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 6.000ns } } }  } 0}
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