i2c.fit.eqn

verilog 编写的I2c协议程序

--A1L09Q is main_state~65 at LC3
A1L09Q_p1_out = !A1L19Q & cnt_delay[18] & cnt_delay[10] & cnt_delay[8] & cnt_delay[19] & !cnt_delay[17] & !cnt_delay[16] & !cnt_delay[15] & !cnt_delay[14] & !cnt_delay[11] & !cnt_delay[9] & !cnt_delay[7] & !cnt_delay[6] & !cnt_delay[5] & !cnt_delay[4] & !cnt_delay[3] & !cnt_delay[2] & !cnt_delay[1] & !cnt_delay[0] & cnt_delay[13] & cnt_delay[12] & !rd_input & wr_input;
A1L09Q_p2_out = !A1L07Q & A1L09Q;
A1L09Q_p3_out = A1L09Q & A1L39 & A1L86Q & !A1L96Q;
A1L09Q_p4_out = A1L09Q & A1L49 & A1L29;
A1L09Q_or_out = A1L09Q_p1_out # A1L09Q_p2_out # A1L09Q_p3_out # A1L09Q_p4_out;
A1L09Q_reg_input = A1L09Q_or_out;
A1L09Q = DFFE(A1L09Q_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--A1L3 is Select~6438 at LC45
A1L3_p0_out = A1L17Q & A1L76Q & A1L86Q & !A1L07Q & A1L051 & phase0;
A1L3_p1_out = A1L76Q & A1L86Q & !A1L07Q & A1L051 & phase0 & A1L27Q;
A1L3_p2_out = A1L17Q & A1L76Q & A1L86Q & A1L051 & phase0 & A1L27Q;
A1L3_p3_out = !A1L17Q & A1L76Q & A1L86Q & A1L07Q & A1L051 & phase0 & !A1L27Q;
A1L3_p4_out = A1L76Q & A1L86Q & A1L051 & phase0 & A1L37Q;
A1L3_or_out = A1L51 # A1L3_p0_out # A1L3_p1_out # A1L3_p2_out # A1L3_p3_out # A1L3_p4_out;
A1L3 = A1L3_or_out;


--A1L4 is Select~6444 at LC31
A1L4_p0_out = A1L96Q & A1L17Q & !phase3 & !A1L07Q & sda_buf;
A1L4_p1_out = A1L96Q & A1L17Q & A1L07Q & A1L051 & phase0;
A1L4_p2_out = A1L96Q & !phase3 & A1L37Q & sda_buf;
A1L4_p3_out = A1L96Q & !A1L17Q & phase3 & A1L37Q & A1L27Q;
A1L4_p4_out = A1L96Q & A1L07Q & sda_buf & !phase0;
A1L4_or_out = A1L71 # A1L4_p0_out # A1L4_p1_out # A1L4_p2_out # A1L4_p3_out # A1L4_p4_out;
A1L4 = A1L4_or_out;


--A1L5 is Select~6450 at LC28
A1L5_p0_out = A1L76Q & !A1L86Q & !phase3 & sda_buf & !phase0;
A1L5_p1_out = A1L76Q & !A1L86Q & A1L07Q & A1L17Q & A1L051 & phase0;
A1L5_p2_out = A1L76Q & !A1L86Q & !phase3 & sda_buf & A1L051;
A1L5_p3_out = A1L76Q & !A1L86Q & A1L07Q & phase3 & A1L17Q;
A1L5_p4_out = A1L76Q & !A1L86Q & A1L07Q & sda_buf & A1L37Q;
A1L5_or_out = A1L81 # A1L5_p0_out # A1L5_p1_out # A1L5_p2_out # A1L5_p3_out # A1L5_p4_out;
A1L5 = A1L5_or_out;


--A1L6 is Select~6456 at LC42
A1L6_p0_out = !A1L76Q & !A1L86Q & !A1L96Q & sda_buf & A1L37Q & !phase3;
A1L6_p1_out = A1L07Q & !A1L17Q & !A1L76Q & !A1L86Q & !A1L96Q & sda_buf;
A1L6_p2_out = !A1L17Q & !A1L76Q & !A1L86Q & !A1L96Q & sda_buf & !A1L27Q & !A1L37Q & !phase1;
A1L6_p3_out = A1L17Q & !A1L76Q & !A1L86Q & !A1L96Q & A1L27Q & !A1L37Q & phase3;
A1L6_p4_out = A1L07Q & A1L17Q & !A1L76Q & !A1L86Q & !A1L96Q & !phase3 & A1L051 & phase0;
A1L6_or_out = A1L91 # A1L6_p0_out # A1L6_p1_out # A1L6_p2_out # A1L6_p3_out # A1L6_p4_out;
A1L6 = A1L6_or_out;


--A1L7 is Select~6462 at LC26
A1L7_p0_out = !A1L76Q & A1L86Q & phase1 & A1L07Q & !phase0 & sda_buf;
A1L7_p1_out = !A1L27Q & !A1L76Q & A1L86Q & A1L37Q & !A1L17Q & phase3 & !writeData_reg[2];
A1L7_p2_out = A1L27Q & !A1L76Q & A1L86Q & A1L37Q & A1L17Q & phase3 & writeData_reg[3];
A1L7_p3_out = !A1L76Q & A1L86Q & A1L17Q & phase1 & A1L07Q & A1L051 & phase0;
A1L7_p4_out = !A1L76Q & A1L86Q & A1L17Q & !phase3 & A1L07Q & A1L051 & phase0;
A1L7_or_out = A1L12 # A1L7_p0_out # A1L7_p1_out # A1L7_p2_out # A1L7_p3_out # A1L7_p4_out;
A1L7 = A1L7_or_out;


--A1L8 is Select~6468 at LC23
A1L8_p0_out = A1L76Q & !A1L86Q & !phase3 & sda_buf & !phase0;
A1L8_p1_out = A1L76Q & !A1L86Q & phase3 & A1L37Q & A1L27Q & A1L17Q;
A1L8_p2_out = A1L76Q & !A1L86Q & !A1L37Q & !A1L17Q & sda_buf;
A1L8_p3_out = A1L76Q & !A1L86Q & phase3 & !A1L37Q & A1L27Q & !A1L17Q & !A1L07Q;
A1L8_p4_out = A1L76Q & !A1L86Q & !phase3 & A1L17Q & A1L07Q & A1L051 & phase0;
A1L8_or_out = A1L22 # A1L8_p0_out # A1L8_p1_out # A1L8_p2_out # A1L8_p3_out # A1L8_p4_out;
A1L8 = A1L8_or_out;


--sda_buf is sda_buf at LC38
sda_buf_p1_out = A1L09Q & !A1L3 & !A1L4 & !A1L5 & !A1L6 & A1L2;
sda_buf_p2_out = !A1L09Q & !A1L6 & !A1L7 & !A1L8 & A1L19Q & A1L9 & A1L01;
sda_buf_or_out = sda_buf_p1_out # sda_buf_p2_out;
sda_buf_reg_input = !(sda_buf_or_out);
sda_buf = DFFE(sda_buf_reg_input, GLOBAL(clk), , rst, );


--readData_reg[0] is readData_reg[0] at LC67
readData_reg[0]_p0_out = !A1L051 & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & A1L37Q & readData_reg[0];
readData_reg[0]_p1_out = A1L051 & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & A1L37Q & !readData_reg[0];
readData_reg[0]_p2_out = !A1L051 & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & readData_reg[0] & A1L27Q;
readData_reg[0]_p3_out = !A1L051 & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & readData_reg[0] & A1L17Q;
readData_reg[0]_p4_out = !A1L051 & phase1 & A1L09Q & A1L76Q & A1L86Q & A1L07Q & readData_reg[0] & !A1L27Q & !A1L17Q;
readData_reg[0]_or_out = A1L151 # readData_reg[0]_p0_out # readData_reg[0]_p1_out # readData_reg[0]_p2_out # readData_reg[0]_p3_out # readData_reg[0]_p4_out;
readData_reg[0]_reg_input = readData_reg[0]_or_out;
readData_reg[0] = TFFE(readData_reg[0]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--readData_reg[1] is readData_reg[1] at LC71
readData_reg[1]_p0_out = !readData_reg[0] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & A1L37Q & readData_reg[1];
readData_reg[1]_p1_out = readData_reg[0] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & A1L37Q & !readData_reg[1];
readData_reg[1]_p2_out = !readData_reg[0] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & readData_reg[1] & A1L27Q;
readData_reg[1]_p3_out = !readData_reg[0] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & readData_reg[1] & A1L17Q;
readData_reg[1]_p4_out = !readData_reg[0] & phase1 & A1L09Q & A1L76Q & A1L86Q & A1L07Q & readData_reg[1] & !A1L27Q & !A1L17Q;
readData_reg[1]_or_out = A1L501 # readData_reg[1]_p0_out # readData_reg[1]_p1_out # readData_reg[1]_p2_out # readData_reg[1]_p3_out # readData_reg[1]_p4_out;
readData_reg[1]_reg_input = readData_reg[1]_or_out;
readData_reg[1] = TFFE(readData_reg[1]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--A1L59 is main_state~608 at SEXP3
A1L59 = EXP(cnt_delay[18] & cnt_delay[10] & cnt_delay[8] & cnt_delay[19] & !cnt_delay[17] & !cnt_delay[16] & !cnt_delay[15] & !cnt_delay[14] & !cnt_delay[11] & !cnt_delay[9] & !cnt_delay[7] & !cnt_delay[6] & !cnt_delay[5] & !cnt_delay[4] & !cnt_delay[3] & !cnt_delay[2] & !cnt_delay[1] & !cnt_delay[0] & cnt_delay[13] & cnt_delay[12]);


--A1L69 is main_state~609 at SEXP1
A1L69 = EXP(A1L86Q & !A1L96Q);


--A1L19Q is main_state~66 at LC2
A1L19Q_p0_out = A1L09Q & A1L07Q & A1L69 & sda_buf & phase1 & A1L17Q;
A1L19Q_p1_out = !A1L09Q & A1L19Q & !A1L86Q & !A1L76Q & A1L96Q;
A1L19Q_p2_out = A1L09Q & A1L86Q & A1L76Q & A1L07Q & A1L27Q & phase3;
A1L19Q_p3_out = !A1L19Q & rd_input & wr_input;
A1L19Q_p4_out = !A1L19Q & A1L59;
A1L19Q_or_out = A1L79 # A1L19Q_p0_out # A1L19Q_p1_out # A1L19Q_p2_out # A1L19Q_p3_out # A1L19Q_p4_out;
A1L19Q_reg_input = !(A1L19Q_or_out);
A1L19Q = DFFE(A1L19Q_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--readData_reg[2] is readData_reg[2] at LC73
readData_reg[2]_p0_out = !readData_reg[1] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & A1L37Q & readData_reg[2];
readData_reg[2]_p1_out = readData_reg[1] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & A1L37Q & !readData_reg[2];
readData_reg[2]_p2_out = !readData_reg[1] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & readData_reg[2] & A1L27Q;
readData_reg[2]_p3_out = !readData_reg[1] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & readData_reg[2] & A1L17Q;
readData_reg[2]_p4_out = !readData_reg[1] & phase1 & A1L09Q & A1L76Q & A1L86Q & A1L07Q & readData_reg[2] & !A1L27Q & !A1L17Q;
readData_reg[2]_or_out = A1L701 # readData_reg[2]_p0_out # readData_reg[2]_p1_out # readData_reg[2]_p2_out # readData_reg[2]_p3_out # readData_reg[2]_p4_out;
readData_reg[2]_reg_input = readData_reg[2]_or_out;
readData_reg[2] = TFFE(readData_reg[2]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--A1L741Q is scl~reg0 at LC40
A1L741Q_p1_out = A1L741Q & !phase2;
A1L741Q_or_out = A1L741Q_p1_out # !A1L19Q # phase0;
A1L741Q_reg_input = A1L741Q_or_out;
A1L741Q = DFFE(A1L741Q_reg_input, GLOBAL(clk), , rst, );


--readData_reg[3] is readData_reg[3] at LC103
readData_reg[3]_p0_out = !readData_reg[2] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & A1L37Q & readData_reg[3];
readData_reg[3]_p1_out = readData_reg[2] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & A1L37Q & !readData_reg[3];
readData_reg[3]_p2_out = !readData_reg[2] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & readData_reg[3] & A1L27Q;
readData_reg[3]_p3_out = !readData_reg[2] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & readData_reg[3] & A1L17Q;
readData_reg[3]_p4_out = !readData_reg[2] & phase1 & A1L09Q & A1L76Q & A1L86Q & A1L07Q & readData_reg[3] & !A1L27Q & !A1L17Q;
readData_reg[3]_or_out = A1L901 # readData_reg[3]_p0_out # readData_reg[3]_p1_out # readData_reg[3]_p2_out # readData_reg[3]_p3_out # readData_reg[3]_p4_out;
readData_reg[3]_reg_input = readData_reg[3]_or_out;
readData_reg[3] = TFFE(readData_reg[3]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--readData_reg[4] is readData_reg[4] at LC101
readData_reg[4]_p0_out = !readData_reg[3] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & A1L37Q & readData_reg[4];
readData_reg[4]_p1_out = readData_reg[3] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & A1L37Q & !readData_reg[4];
readData_reg[4]_p2_out = !readData_reg[3] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & readData_reg[4] & A1L27Q;
readData_reg[4]_p3_out = !readData_reg[3] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & readData_reg[4] & A1L17Q;
readData_reg[4]_p4_out = !readData_reg[3] & phase1 & A1L09Q & A1L76Q & A1L86Q & A1L07Q & readData_reg[4] & !A1L27Q & !A1L17Q;
readData_reg[4]_or_out = A1L111 # readData_reg[4]_p0_out # readData_reg[4]_p1_out # readData_reg[4]_p2_out # readData_reg[4]_p3_out # readData_reg[4]_p4_out;
readData_reg[4]_reg_input = readData_reg[4]_or_out;
readData_reg[4] = TFFE(readData_reg[4]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--readData_reg[5] is readData_reg[5] at LC105
readData_reg[5]_p0_out = !readData_reg[4] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & A1L37Q & readData_reg[5];
readData_reg[5]_p1_out = readData_reg[4] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & A1L37Q & !readData_reg[5];
readData_reg[5]_p2_out = !readData_reg[4] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & readData_reg[5] & A1L27Q;
readData_reg[5]_p3_out = !readData_reg[4] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & readData_reg[5] & A1L17Q;
readData_reg[5]_p4_out = !readData_reg[4] & phase1 & A1L09Q & A1L76Q & A1L86Q & A1L07Q & readData_reg[5] & !A1L27Q & !A1L17Q;
readData_reg[5]_or_out = A1L311 # readData_reg[5]_p0_out # readData_reg[5]_p1_out # readData_reg[5]_p2_out # readData_reg[5]_p3_out # readData_reg[5]_p4_out;
readData_reg[5]_reg_input = readData_reg[5]_or_out;
readData_reg[5] = TFFE(readData_reg[5]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--readData_reg[6] is readData_reg[6] at LC112
readData_reg[6]_p0_out = !readData_reg[5] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & A1L37Q & readData_reg[6];
readData_reg[6]_p1_out = readData_reg[5] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & A1L37Q & !readData_reg[6];
readData_reg[6]_p2_out = !readData_reg[5] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & readData_reg[6] & A1L27Q;
readData_reg[6]_p3_out = !readData_reg[5] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & readData_reg[6] & A1L17Q;
readData_reg[6]_p4_out = !readData_reg[5] & phase1 & A1L09Q & A1L76Q & A1L86Q & A1L07Q & readData_reg[6] & !A1L27Q & !A1L17Q;
readData_reg[6]_or_out = A1L511 # readData_reg[6]_p0_out # readData_reg[6]_p1_out # readData_reg[6]_p2_out # readData_reg[6]_p3_out # readData_reg[6]_p4_out;
readData_reg[6]_reg_input = readData_reg[6]_or_out;
readData_reg[6] = TFFE(readData_reg[6]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--readData_reg[7] is readData_reg[7] at LC110
readData_reg[7]_p0_out = !readData_reg[6] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & A1L37Q & readData_reg[7];
readData_reg[7]_p1_out = readData_reg[6] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & A1L37Q & !readData_reg[7];
readData_reg[7]_p2_out = !readData_reg[6] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & readData_reg[7] & A1L27Q;
readData_reg[7]_p3_out = !readData_reg[6] & phase1 & A1L09Q & A1L76Q & A1L86Q & !A1L07Q & readData_reg[7] & A1L17Q;
readData_reg[7]_p4_out = !readData_reg[6] & phase1 & A1L09Q & A1L76Q & A1L86Q & A1L07Q & readData_reg[7] & !A1L27Q & !A1L17Q;
readData_reg[7]_or_out = A1L711 # readData_reg[7]_p0_out # readData_reg[7]_p1_out # readData_reg[7]_p2_out # readData_reg[7]_p3_out # readData_reg[7]_p4_out;
readData_reg[7]_reg_input = readData_reg[7]_or_out;
readData_reg[7] = TFFE(readData_reg[7]_reg_input, GLOBAL(clk), GLOBAL(rst), , );


--A1L911 is reduce_or~2464 at LC108
A1L911_p0_out = A1L46Q & readData_reg[7];
A1L911_p1_out = A1L66Q & writeData_reg[1] & !writeData_reg[3] & !writeData_reg[2] & !writeData_reg[0];
A1L911_p2_out = !A1L66Q & readData_reg[2] & !readData_reg[1] & readData_reg[3] & !readData_reg[0];
A1L911_p3_out = readData_reg[2] & readData_reg[1] & !readData_reg[3] & readData_reg[0] & A1L46Q;
A1L911_p4_out = !A1L66Q & !A1L46Q;
A1L911_or_out = A1L731 # A1L911_p0_out # A1L911_p1_out # A1L911_p2_out # A1L911_p3_out # A1L911_p4_out;
A1L911 = A1L911_or_out;


--A1L021 is reduce_or~2465 at SEXP96
A1L021 = EXP(readData_reg[1] & !readData_reg[2]);


--A1L121 is reduce_or~2466 at SEXP95
A1L121 = EXP(!readData_reg[1] & readData_reg[2]);


--A1L221 is reduce_or~2467 at SEXP89
A1L221 = EXP(!writeData_reg[2] & !writeData_reg[1]);


--A1L321 is reduce_or~2468 at SEXP83
A1L321 = EXP(writeData_reg[2] & writeData_reg[1]);


--A1L421 is reduce_or~2469 at SEXP82
A1L421 = EXP(!readData_reg[1] & !readData_reg[4] & !readData_reg[5] & !readData_reg[6] & !readData_reg[7] & readData_reg[2] & A1L46Q & !readData_reg[3]);


--A1L521 is reduce_or~2470 at SEXP81
A1L521 = EXP(!A1L46Q & !A1L66Q);


--A1L621 is reduce_or~2471 at SEXP94
A1L621 = EXP(A1L46Q & A1L66Q);


--A1L721 is reduce_or~2472 at SEXP92
A1L721 = EXP(!writeData_reg[2] & !writeData_reg[3] & !writeData_reg[1] & !A1L46Q);


--A1L821 is reduce_or~2477 at LC86
A1L821_p1_out = A1L421 & A1L521 & A1L621 & A1L721;
A1L821_p0_out = A1L421 & A1L521 & A1L621 & A1L721 & !A1L46Q & A1L321 & writeData_reg[0];
A1L821_p2_out = A1L421 & A1L521 & A1L621 & A1L721 & A1L021 & !readData_reg[4] & !readData_reg[5] & !readData_reg[6] & !readData_reg[7] & !readData_reg[0] & A1L46Q;
A1L821_p3_out = A1L421 & A1L521 & A1L621 & A1L721 & !readData_reg[4] & !readData_reg[5] & !readData_reg[6] & !readData_reg[7] & A1L46Q & A1L121 & readData_reg[3];
A1L821_p4_out = A1L421 & A1L521 & A1L621 & A1L721 & !A1L46Q & A1L221 & writeData_reg[3];
A1L821_or_out = A1L821_p0_out # A1L821_p2_out # A1L821_p3_out # A1L821_p4_out;
A1L821 = A1L821_p1_out $ A1L821_or_out;


--A1L921 is reduce_or~2480 at SEXP99
A1L921 = EXP(!readData_reg[4] & !readData_reg[5] & !readData_reg[6] & !readData_reg[7]);