📄 d4_16.rpt
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cpldfit: version F.31 Xilinx Inc.
Fitter Report
Design Name: d4_16 Date: 8-11-2004, 10:34AM
Device Used: XC95144-7-PQ100
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
16 /144 ( 11%) 16 /720 ( 2%) 0 /144 ( 0%) 22 /81 ( 27%) 48 /288 ( 17%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 6 6 | I/O : 22 51
Output : 16 16 | GCK/IO : 0 3
Bidirectional : 0 0 | GTS/IO : 0 4
GCK : 0 0 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 22 22
MACROCELL RESOURCES:
Total Macrocells Available 144
Registered Macrocells 0
Non-registered Macrocell driving I/O 16
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 16 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 16 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init
Name Pt Used Mode Rate # Type Use State
cs_out<0> 1 6 FB3_5 STD FAST 26 I/O O
cs_out<10> 1 6 FB4_2 STD FAST 89 I/O O
cs_out<11> 1 6 FB5_2 STD FAST 37 I/O O
cs_out<12> 1 6 FB6_2 STD FAST 76 I/O O
cs_out<13> 1 6 FB7_2 STD FAST 52 I/O O
cs_out<14> 1 6 FB8_2 STD FAST 65 I/O O
cs_out<15> 1 6 FB4_11 STD FAST 95 I/O O
cs_out<1> 1 6 FB6_11 STD FAST 82 I/O O
cs_out<2> 1 6 FB1_2 STD FAST 13 I/O O
cs_out<3> 1 6 FB1_6 STD FAST 16 I/O O
cs_out<4> 1 6 FB1_11 STD FAST 19 I/O O
cs_out<5> 1 6 FB3_12 STD FAST 32 I/O O
cs_out<6> 1 6 FB5_11 STD FAST 43 I/O O
cs_out<7> 1 6 FB7_11 STD FAST 58 I/O O
cs_out<8> 1 6 FB2_11 STD FAST 8 I/O O
cs_out<9> 1 6 FB2_15 STD FAST 11 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
cs FB4_17 99 I/O I
din<0> FB8_11 70 I/O I
din<1> FB3_11 31 I/O I
din<2> FB4_14 97 I/O I
din<3> FB3_14 34 I/O I
reset FB8_5 66 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 3 6 6 3 3/0 11
FB2 2 6 6 2 2/0 10
FB3 2 6 6 2 2/0 10
FB4 2 6 6 2 2/0 10
FB5 2 6 6 2 2/0 10
FB6 2 6 6 2 2/0 10
FB7 2 6 6 2 2/0 10
FB8 1 6 6 1 1/0 10
---- ----- ----- -----
16 16 16/0 81
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 6/30
Number of signals used by logic mapping into function block: 6
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 (b)
cs_out<2> 1 0 0 4 FB1_2 STD 13 I/O O
(unused) 0 0 0 5 FB1_3 14 I/O
(unused) 0 0 0 5 FB1_4 (b)
(unused) 0 0 0 5 FB1_5 15 I/O
cs_out<3> 1 0 0 4 FB1_6 STD 16 I/O O
(unused) 0 0 0 5 FB1_7 (b)
(unused) 0 0 0 5 FB1_8 17 I/O
(unused) 0 0 0 5 FB1_9 18 I/O
(unused) 0 0 0 5 FB1_10 (b)
cs_out<4> 1 0 0 4 FB1_11 STD 19 I/O O
(unused) 0 0 0 5 FB1_12 20 I/O
(unused) 0 0 0 5 FB1_13 (b)
(unused) 0 0 0 5 FB1_14 21 I/O
(unused) 0 0 0 5 FB1_15 22 I/O
(unused) 0 0 0 5 FB1_16 (b)
(unused) 0 0 0 5 FB1_17 24 GCK/I/O
(unused) 0 0 0 5 FB1_18 (b)
Signals Used by Logic in Function Block
1: cs 3: din<1> 5: din<3>
2: din<0> 4: din<2> 6: reset
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
cs_out<2> XXXXXX.................................. 6 6
cs_out<3> XXXXXX.................................. 6 6
cs_out<4> XXXXXX.................................. 6 6
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 6/30
Number of signals used by logic mapping into function block: 6
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 (b)
(unused) 0 0 0 5 FB2_2 1 GSR/I/O
(unused) 0 0 0 5 FB2_3 (b)
(unused) 0 0 0 5 FB2_4 (b)
(unused) 0 0 0 5 FB2_5 3 GTS/I/O
(unused) 0 0 0 5 FB2_6 4 GTS/I/O
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 5 GTS/I/O
(unused) 0 0 0 5 FB2_9 6 GTS/I/O
(unused) 0 0 0 5 FB2_10 (b)
cs_out<8> 1 0 0 4 FB2_11 STD 8 I/O O
(unused) 0 0 0 5 FB2_12 9 I/O
(unused) 0 0 0 5 FB2_13 (b)
(unused) 0 0 0 5 FB2_14 10 I/O
cs_out<9> 1 0 0 4 FB2_15 STD 11 I/O O
(unused) 0 0 0 5 FB2_16 (b)
(unused) 0 0 0 5 FB2_17 12 I/O
(unused) 0 0 0 5 FB2_18 (b)
Signals Used by Logic in Function Block
1: cs 3: din<1> 5: din<3>
2: din<0> 4: din<2> 6: reset
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
cs_out<8> XXXXXX.................................. 6 6
cs_out<9> XXXXXX.................................. 6 6
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 6/30
Number of signals used by logic mapping into function block: 6
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB3_1 (b)
(unused) 0 0 0 5 FB3_2 25 GCK/I/O
(unused) 0 0 0 5 FB3_3 (b)
(unused) 0 0 0 5 FB3_4 (b)
cs_out<0> 1 0 0 4 FB3_5 STD 26 I/O O
(unused) 0 0 0 5 FB3_6 27 I/O
(unused) 0 0 0 5 FB3_7 (b)
(unused) 0 0 0 5 FB3_8 29 GCK/I/O
(unused) 0 0 0 5 FB3_9 30 I/O
(unused) 0 0 0 5 FB3_10 (b)
(unused) 0 0 0 5 FB3_11 31 I/O I
cs_out<5> 1 0 0 4 FB3_12 STD 32 I/O O
(unused) 0 0 0 5 FB3_13 (b)
(unused) 0 0 0 5 FB3_14 34 I/O I
(unused) 0 0 0 5 FB3_15 35 I/O
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