d4_16.rpt
来自「此文件是对xilinx95144器件编的程序」· RPT 代码 · 共 626 行 · 第 1/3 页
RPT
626 行
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB8 ***********************************
Number of function block inputs used/remaining: 6/30
Number of signals used by logic mapping into function block: 6
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB8_1 (b)
cs_out<14> 1 0 0 4 FB8_2 STD 65 I/O O
(unused) 0 0 0 5 FB8_3 (b)
(unused) 0 0 0 5 FB8_4 (b)
(unused) 0 0 0 5 FB8_5 66 I/O I
(unused) 0 0 0 5 FB8_6 67 I/O
(unused) 0 0 0 5 FB8_7 (b)
(unused) 0 0 0 5 FB8_8 68 I/O
(unused) 0 0 0 5 FB8_9 69 I/O
(unused) 0 0 0 5 FB8_10 (b)
(unused) 0 0 0 5 FB8_11 70 I/O I
(unused) 0 0 0 5 FB8_12 72 I/O
(unused) 0 0 0 5 FB8_13 (b)
(unused) 0 0 0 5 FB8_14 73 I/O
(unused) 0 0 0 5 FB8_15 74 I/O
(unused) 0 0 0 5 FB8_16 (b)
(unused) 0 0 0 5 FB8_17 75 I/O
(unused) 0 0 0 5 FB8_18 (b)
Signals Used by Logic in Function Block
1: cs 3: din<1> 5: din<3>
2: din<0> 4: din<2> 6: reset
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
cs_out<14> XXXXXX.................................. 6 6
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
!cs_out<0> = !(cs) & !(reset) & !(din<3>) & !(din<2>) & !(din<1>) &
!(din<0>);
!cs_out<10> = !(cs) & !(reset) & din<3> & !(din<2>) & din<1> &
!(din<0>);
!cs_out<11> = !(cs) & !(reset) & din<3> & !(din<2>) & din<1> &
din<0>;
!cs_out<12> = !(cs) & !(reset) & din<3> & din<2> & !(din<1>) &
!(din<0>);
!cs_out<13> = !(cs) & !(reset) & din<3> & din<2> & !(din<1>) &
din<0>;
!cs_out<14> = !(cs) & !(reset) & din<3> & din<2> & din<1> &
!(din<0>);
!cs_out<15> = !(cs) & !(reset) & din<3> & din<2> & din<1> &
din<0>;
!cs_out<1> = !(cs) & !(reset) & !(din<3>) & !(din<2>) & !(din<1>) &
din<0>;
!cs_out<2> = !(cs) & !(reset) & !(din<3>) & !(din<2>) & din<1> &
!(din<0>);
!cs_out<3> = !(cs) & !(reset) & !(din<3>) & !(din<2>) & din<1> &
din<0>;
!cs_out<4> = !(cs) & !(reset) & !(din<3>) & din<2> & !(din<1>) &
!(din<0>);
!cs_out<5> = !(cs) & !(reset) & !(din<3>) & din<2> & !(din<1>) &
din<0>;
!cs_out<6> = !(cs) & !(reset) & !(din<3>) & din<2> & din<1> &
!(din<0>);
!cs_out<7> = !(cs) & !(reset) & !(din<3>) & din<2> & din<1> &
din<0>;
!cs_out<8> = !(cs) & !(reset) & din<3> & !(din<2>) & !(din<1>) &
!(din<0>);
!cs_out<9> = !(cs) & !(reset) & din<3> & !(din<2>) & !(din<1>) &
din<0>;
**************************** Device Pin Out ****************************
Device : XC95144-7-PQ100
c c
s s c
_ _ s
o o _
d u u o
i t t u
n < < t
V T < T 1 T T T T V 1 T T G T T T < T
C c I 2 I 5 I I I I C 0 I I N D I I 1 I
C s E > E > E E E E C > E E D O E E > E
----------------------------------------
/100 98 96 94 92 90 88 86 84 82 \
| 99 97 95 93 91 89 87 85 83 81 |
TIE | 1 80 | TIE
GND | 2 79 | TIE
TIE | 3 78 | TIE
TIE | 4 77 | GND
TIE | 5 76 | cs_out<12>
TIE | 6 75 | TIE
VCC | 7 74 | TIE
cs_out<8> | 8 73 | TIE
TIE | 9 72 | TIE
TIE | 10 71 | GND
cs_out<9> | 11 70 | din<0>
TIE | 12 69 | TIE
cs_out<2> | 13 XC95144-7-PQ100 68 | TIE
TIE | 14 67 | TIE
TIE | 15 66 | reset
cs_out<3> | 16 65 | cs_out<14>
TIE | 17 64 | GND
TIE | 18 63 | TIE
cs_out<4> | 19 62 | TIE
TIE | 20 61 | TIE
TIE | 21 60 | TIE
TIE | 22 59 | VCC
GND | 23 58 | cs_out<7>
TIE | 24 57 | TIE
TIE | 25 56 | TIE
cs_out<0> | 26 55 | TIE
TIE | 27 54 | TIE
VCC | 28 53 | VCC
TIE | 29 52 | cs_out<13>
TIE | 30 51 | TIE
| 32 34 36 38 40 42 44 46 48 50 |
\31 33 35 37 39 41 43 45 47 49 /
----------------------------------------
d c G d T T c T T V T T c T T G T T T T
i s N i I I s I I C I I s I I N D I M C
n _ D n E E _ E E C E E _ E E D I E S K
< o < o o
1 u 3 u u
> t > t t
< < <
5 1 6
> 1 >
>
Legend : NC = Not Connected, unbonded pin
PGND = Unused I/O configured as additional Ground pin
TIE = Unused I/O floating -- must tie to VCC, GND or other signal
VCC = Dedicated Power Pin
GND = Dedicated Ground Pin
TDI = Test Data In, JTAG pin
TDO = Test Data Out, JTAG pin
TCK = Test Clock, JTAG pin
TMS = Test Mode Select, JTAG pin
PE = Port Enable pin
PROHIBITED = User reserved pin
**************************** Compiler Options ****************************
Following is a list of all global compiler options used by the fitter run.
Device(s) Specified : XC95144-7-PQ100
Optimization Method : SPEED
Multi-Level Logic Optimization : ON
Ignore Timing Specifications : OFF
Default Register Power Up Value : LOW
Slew Rate : FAST
Keep User Location Constraints : ON
What-You-See-Is-What-You-Get : OFF
Exhaustive Fitting : OFF
Keep Unused Inputs : OFF
Power Mode : STD
Ground on Unused IOs : OFF
Global Clock Optimization : ON
Global Set/Reset Optimization : ON
Global Ouput Enable Optimization : ON
FASTConnect/UIM optimzation : ON
Local Feedback : ON
Pin Feedback : ON
Input Limit : 36
Pterm Limit : 25
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