basketball.v

来自「一个小程序」· Verilog 代码 · 共 34 行

module basketball (CPB,L,QH,QL,CPA,S,LD,CR);
output [3:0]QH,QL;
output CPB,L;
input S,LD,CR;
input CPA;
reg [3:0] QH;
reg [3:0] QL;
reg CPB;
reg L;
reg [3:0]i;
reg QC;
always @(posedge CPA)
begin
if (S==0) CPB<=CPB;
else if(i==9)
begin i=0;CPB<=1;end
else
begin i=i+1;CPB<=0;end
end
always @ (posedge CPB or negedge LD or negedge CR)
begin
if (!CR) begin QH[3:0]<=0;QL[3:0]<=0;QC<=0;end
else 
if (!LD) begin QH[3:0]<=0;QL[3:0]<=0;QC<=1;L=0;end
else if(QH==0&QL==0)
begin QH[3:0]<=0;QL[3:0]<=0;L=QC;end
else if (QL[3:0]==0)
begin QL[3:0]<=9;QH[3:0]<=QH[3:0]-1;end
else 
begin QL[3:0]<=QL[3:0]-1;QH[3:0]<=QH[3:0];end
end
endmodule