top.vhd

基于FPGA液晶控制器设计与实现（VHDL语言）

-- -----------------------------------------------------------------------------
--
-- 文件名 : top.vhd
--
-- 功能   : 顶层文件,包含 reset, pll, lcd, threadCPU 模块.
--
-- 端口   : CLK        : in   PIN_28,  外部 50MHz 晶振.
--          nRESET    : in    PIN_124, 外部 复位按键.
--
--          lcd_RS    : out   PIN_176, 1602 LCD 的 RS 管脚.
--          lcd_RW    : out   PIN_179, 1602 LCD 的 RW 管脚.
--          lcd_E     : out   PIN_178, 1602 LCD 的 E  管脚.
--          lcd_D0    : out   PIN_177, 1602 LCD 的 D0 管脚.
--          lcd_D1    : out   PIN_174, 1602 LCD 的 D1 管脚.
--          lcd_D2    : out   PIN_175, 1602 LCD 的 D2 管脚.
--          lcd_D3    : out   PIN_170, 1602 LCD 的 D3 管脚.
--          lcd_D4    : out   PIN_173, 1602 LCD 的 D4 管脚.
--          lcd_D5    : out   PIN_168, 1602 LCD 的 D5 管脚.
--          lcd_D6    : out   PIN_169, 1602 LCD 的 D6 管脚.
--          lcd_D7    : out   PIN_166, 1602 LCD 的 D7 管脚.
--
-- 笔记   : 1.nRESET 为低电平有效,即 按下 RESET 键.
--
-- Total logic elements:  /12,060 ( %)
-- Total memory bits   :  /239,616( %)
-- -----------------------------------------------------------------------------
-- 建立日期 : 2007/4/15
-- -----------------------------------------------------------------------------
-- 修改日期 :
-- 修改内容 :
-- -----------------------------------------------------------------------------

library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_unsigned.all;

entity top is
	port (
		CLK              : in  std_logic;

		nRESET           : in  std_logic;

		-----------  LCD 显示 --------------------
		lcd_RS           : out std_logic;
		lcd_RW           : out std_logic;
		lcd_E            : out std_logic;
		lcd_Data         : out std_logic_vector(7 downto 0)
	);
end top;

architecture RTL of top is
----------------------------------------------------------
	component reset is
		port
		(
			CLK         : in std_logic  := '0';
			CLK_Z       : in std_logic  := '0';
			pulse1K     : in std_logic;

			CLK_EN      : in std_logic;
			nRESET      : in  std_logic;

			RESET       : out std_logic
		);
	end component;

	component clockGroups is
		port
		(
			CLK         : in std_logic  := '0';

			CLK_EN      : out std_logic;

			CLK_Z       : out std_logic;
			CLK_H       : out std_logic;

			pulse1K     : out std_logic;
			pulse1M     : out std_logic
		);
	end component;

	component lcd is
		port (
			CLK_Z            : in  std_logic;
			pulse1K          : in  std_logic;
			pulse1M          : in  std_logic;

			RESET            : in  std_logic;

			enable           : in  std_logic;
			wren             : in  std_logic;
			writeAddr        : in  std_logic_vector(2 downto 0);
			writeData        : in  std_logic_vector(15 downto 0);

			lcd_RS           : out std_logic;
			lcd_RW           : out std_logic;
			lcd_E            : out std_logic;
			lcd_Data         : out std_logic_vector(7 downto 0)
		);
	end component;


	component lcd_test is
		port (
			CLK_Z            : in  std_logic;
			pulse1K          : in  std_logic;

			RESET            : in  std_logic;

			enable           : out std_logic;
			wren             : out std_logic;
			writeAddr        : out std_logic_vector(2 downto 0);
			writeData        : out std_logic_vector(15 downto 0)
		);
	end component;

	----------------------------------------------------------------------------------------
	signal CLK_Z,   CLK_H              : std_logic;
	signal pulse1K, pulse1M            : std_logic;
	signal CLK_EN                      : std_logic;
	signal tempRESET                       : std_logic;

	signal writeAddr                   : std_logic_vector(2 downto 0);
	signal writeData                   : std_logic_vector(15 downto 0);

	signal enable, wren                : std_logic;

begin
	p_reset_comb : reset
		port map(
			CLK          => CLK,
			CLK_Z        => CLK_Z,
			pulse1K      => pulse1K,

			CLK_EN       => CLK_EN,
			nRESET       => nRESET,
			RESET        => tempRESET
		);

	p_clockGroups_comb : clockGroups
		port map(
			CLK          => CLK,
			CLK_EN       => CLK_EN,
			CLK_H        => CLK_H,
			CLK_Z        => CLK_Z,
			pulse1K      => pulse1K,
			pulse1M      => pulse1M
		);

	p_lcd_comb : lcd
		port map(
			CLK_Z            => CLK_Z,
			pulse1K          => pulse1K,
			pulse1M          => pulse1M,

			RESET            => tempRESET,

			enable           => enable,
			wren             => wren,
			writeAddr        => writeAddr,
			writeData        => writeData,

			lcd_RS           => lcd_RS,
			lcd_RW           => lcd_RW,
			lcd_E            => lcd_E,
			lcd_Data         => lcd_Data
		);

	p_lcd_test_comb : lcd_test
		port map (
			CLK_Z          => CLK_Z,
			pulse1K        => pulse1K,

			RESET          => tempRESET,

			enable         => enable,
			wren           => wren,

			writeAddr      => writeAddr,
			writeData      => writeData
		);

end rtl;