top.map.summary

来自「基于FPGA液晶控制器设计与实现（VHDL语言）」· SUMMARY 代码 · 共 11 行

Analysis & Synthesis Status : Successful - Wed Apr 18 03:41:09 2007
Quartus II Version : 5.1 Build 176 10/26/2005 SJ Full Version
Revision Name : top
Top-level Entity Name : top
Family : Cyclone
Total logic elements : 403
Total pins : 13
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 1