top.map.rpt

基于FPGA液晶控制器设计与实现（VHDL语言）

; PORT_INCLK1                   ; PORT_CONNECTIVITY ; Untyped                                                           ;
; PORT_INCLK0                   ; PORT_CONNECTIVITY ; Untyped                                                           ;
; PORT_FBIN                     ; PORT_CONNECTIVITY ; Untyped                                                           ;
; PORT_PLLENA                   ; PORT_CONNECTIVITY ; Untyped                                                           ;
; PORT_CLKSWITCH                ; PORT_CONNECTIVITY ; Untyped                                                           ;
; PORT_ARESET                   ; PORT_CONNECTIVITY ; Untyped                                                           ;
; PORT_PFDENA                   ; PORT_CONNECTIVITY ; Untyped                                                           ;
; PORT_SCANCLK                  ; PORT_CONNECTIVITY ; Untyped                                                           ;
; PORT_SCANACLR                 ; PORT_CONNECTIVITY ; Untyped                                                           ;
; PORT_SCANREAD                 ; PORT_CONNECTIVITY ; Untyped                                                           ;
; PORT_SCANWRITE                ; PORT_CONNECTIVITY ; Untyped                                                           ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY ; Untyped                                                           ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY ; Untyped                                                           ;
; M_TEST_SOURCE                 ; 5                 ; Untyped                                                           ;
; C0_TEST_SOURCE                ; 5                 ; Untyped                                                           ;
; C1_TEST_SOURCE                ; 5                 ; Untyped                                                           ;
; C2_TEST_SOURCE                ; 5                 ; Untyped                                                           ;
; C3_TEST_SOURCE                ; 5                 ; Untyped                                                           ;
; C4_TEST_SOURCE                ; 5                 ; Untyped                                                           ;
; C5_TEST_SOURCE                ; 5                 ; Untyped                                                           ;
; DEVICE_FAMILY                 ; Cyclone           ; Untyped                                                           ;
; AUTO_CARRY_CHAINS             ; ON                ; AUTO_CARRY                                                        ;
; IGNORE_CARRY_BUFFERS          ; OFF               ; IGNORE_CARRY                                                      ;
; AUTO_CASCADE_CHAINS           ; ON                ; AUTO_CASCADE                                                      ;
; IGNORE_CASCADE_BUFFERS        ; OFF               ; IGNORE_CASCADE                                                    ;
+-------------------------------+-------------------+-------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/FPGA/top/top.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Wed Apr 18 03:41:00 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top -c top
Info: Found 2 design units, including 1 entities, in source file clockGroups.vhd
    Info: Found design unit 1: clockGroups-SYN
    Info: Found entity 1: clockGroups
Info: Found 2 design units, including 1 entities, in source file lcd.vhd
    Info: Found design unit 1: lcd-RTL
    Info: Found entity 1: lcd
Info: Found 2 design units, including 1 entities, in source file lcd_test.vhd
    Info: Found design unit 1: lcd_test-RTL
    Info: Found entity 1: lcd_test
Info: Found 2 design units, including 1 entities, in source file reset.vhd
    Info: Found design unit 1: reset-rtl
    Info: Found entity 1: reset
Info: Found 2 design units, including 1 entities, in source file systemPLL.vhd
    Info: Found design unit 1: systempll-SYN
    Info: Found entity 1: systemPLL
Info: Found 2 design units, including 1 entities, in source file top.vhd
    Info: Found design unit 1: top-RTL
    Info: Found entity 1: top
Info: Elaborating entity "top" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at top.vhd(119): object "CLK_H" assigned a value but never read
Info: Elaborating entity "reset" for hierarchy "reset:p_reset_comb"
Info: Elaborating entity "clockGroups" for hierarchy "clockGroups:p_clockGroups_comb"
Info: Elaborating entity "systemPLL" for hierarchy "clockGroups:p_clockGroups_comb|systemPLL:pll_pro"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/altpll.tdf
    Info: Found entity 1: altpll
Info: Elaborating entity "altpll" for hierarchy "clockGroups:p_clockGroups_comb|systemPLL:pll_pro|altpll:altpll_component"
Info: Elaborating entity "lcd" for hierarchy "lcd:p_lcd_comb"
Info (10425): VHDL Case Statement information at lcd.vhd(137): OTHERS choice is never selected
Info (10425): VHDL Case Statement information at lcd.vhd(158): OTHERS choice is never selected
Info (10425): VHDL Case Statement information at lcd.vhd(262): OTHERS choice is never selected
Info: Elaborating entity "lcd_test" for hierarchy "lcd_test:p_lcd_test_comb"
Info: Duplicate registers merged to single register
    Info: Duplicate register "lcd_test:p_lcd_test_comb|lcdData[0]" merged to single register "lcd_test:p_lcd_test_comb|lcdAddr[0]"
    Info: Duplicate register "lcd_test:p_lcd_test_comb|lcdData[1]" merged to single register "lcd_test:p_lcd_test_comb|lcdAddr[1]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "lcd_test:p_lcd_test_comb|lcdAddr[2]" merged to single register "lcd_test:p_lcd_test_comb|lcdData[2]"
    Info: Duplicate register "lcd:p_lcd_comb|tempRamData0[0]" merged to single register "lcd:p_lcd_comb|tempRamData0[1]"
    Info: Duplicate register "lcd:p_lcd_comb|tempRamData4[0]" merged to single register "lcd:p_lcd_comb|tempRamData4[1]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "lcd:p_lcd_comb|tempRamData0[1]" merged to single register "lcd:p_lcd_comb|tempRamData0[2]"
    Info: Duplicate register "lcd:p_lcd_comb|tempRamData1[1]" merged to single register "lcd:p_lcd_comb|tempRamData1[2]"
    Info: Duplicate register "lcd:p_lcd_comb|tempRamData2[0]" merged to single register "lcd:p_lcd_comb|tempRamData2[2]"
    Info: Duplicate register "lcd:p_lcd_comb|tempRamData7[0]" merged to single register "lcd:p_lcd_comb|tempRamData7[1]"
Warning: Reduced register "lcd:p_lcd_comb|tempRamData0[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "lcd:p_lcd_comb|tempRamData4[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "lcd:p_lcd_comb|tempRamData2[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "lcd:p_lcd_comb|tempRamData6[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "lcd:p_lcd_comb|tempRamData1[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "lcd:p_lcd_comb|tempRamData3[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "lcd:p_lcd_comb|tempRamData5[1]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "lcd:p_lcd_comb|tempRamData7[2]" merged to single register "lcd:p_lcd_comb|tempRamData7[1]"
    Info: Duplicate register "lcd:p_lcd_comb|tempRamData3[1]" merged to single register "lcd:p_lcd_comb|tempRamData3[0]"
    Info: Duplicate register "lcd:p_lcd_comb|tempRamData5[2]" merged to single register "lcd:p_lcd_comb|tempRamData5[0]"
    Info: Duplicate register "lcd:p_lcd_comb|tempRamData6[1]" merged to single register "lcd:p_lcd_comb|tempRamData6[2]"
Info: State machine "|top|lcd:p_lcd_comb|stateS" contains 11 states
Info: Selected Auto state machine encoding method for state machine "|top|lcd:p_lcd_comb|stateS"
Info: Encoding result for state machine "|top|lcd:p_lcd_comb|stateS"
    Info: Completed encoding using 11 state bits
        Info: Encoded state bit "lcd:p_lcd_comb|stateS.sdata3"
        Info: Encoded state bit "lcd:p_lcd_comb|stateS.sdata2"
        Info: Encoded state bit "lcd:p_lcd_comb|stateS.sdata1"
        Info: Encoded state bit "lcd:p_lcd_comb|stateS.sdata0"
        Info: Encoded state bit "lcd:p_lcd_comb|stateS.saddr"
        Info: Encoded state bit "lcd:p_lcd_comb|stateS.sinit5"
        Info: Encoded state bit "lcd:p_lcd_comb|stateS.sinit4"
        Info: Encoded state bit "lcd:p_lcd_comb|stateS.sinit3"
        Info: Encoded state bit "lcd:p_lcd_comb|stateS.sinit2"
        Info: Encoded state bit "lcd:p_lcd_comb|stateS.sinit1"
        Info: Encoded state bit "lcd:p_lcd_comb|stateS.sinit0"
    Info: State "|top|lcd:p_lcd_comb|stateS.sinit0" uses code string "00000000000"
    Info: State "|top|lcd:p_lcd_comb|stateS.sinit1" uses code string "00000000011"
    Info: State "|top|lcd:p_lcd_comb|stateS.sinit2" uses code string "00000000101"
    Info: State "|top|lcd:p_lcd_comb