top.fit.rpt

基于FPGA液晶控制器设计与实现（VHDL语言）

; Enable Bus-Hold Circuitry                            ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                   ; Off                            ; Off                            ;
; Auto Packed Registers -- Cyclone                     ; Auto                           ; Auto                           ;
; Auto Delay Chains                                    ; On                             ; On                             ;
; Auto Merge PLLs                                      ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic   ; Off                            ; Off                            ;
; Perform Register Duplication                         ; Off                            ; Off                            ;
; Perform Register Retiming                            ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining               ; Off                            ; Off                            ;
; Fitter Effort                                        ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                      ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication             ; Auto                           ; Auto                           ;
; Auto Register Duplication                            ; Off                            ; Off                            ;
; Auto Global Clock                                    ; On                             ; On                             ;
; Auto Global Register Control Signals                 ; On                             ; On                             ;
+------------------------------------------------------+--------------------------------+--------------------------------+


+--------------------------------------------------------------------+
; Fitter Device Options                                              ;
+----------------------------------------------+---------------------+
; Option                                       ; Setting             ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                 ;
; Enable device-wide reset (DEV_CLRn)          ; Off                 ;
; Enable device-wide output enable (DEV_OE)    ; Off                 ;
; Enable INIT_DONE output                      ; Off                 ;
; Configuration scheme                         ; Active Serial       ;
; Error detection CRC                          ; Off                 ;
; Reserve all unused pins                      ; As input tri-stated ;
; Base pin-out file on sameframe device        ; Off                 ;
+----------------------------------------------+---------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in E:/FPGA/top/top.fit.eqn.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/FPGA/top/top.pin.


+------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                                                                                ;
+---------------------------------------------+--------------------------------------------------------------------------------+
; Resource                                    ; Usage                                                                          ;
+---------------------------------------------+--------------------------------------------------------------------------------+
; Total logic elements                        ; 340 / 12,060 ( 3 % )                                                           ;
;     -- Combinational with no register       ; 114                                                                            ;
;     -- Register only                        ; 71                                                                             ;
;     -- Combinational with a register        ; 155                                                                            ;
;                                             ;                                                                                ;
; Logic element usage by number of LUT inputs ;                                                                                ;
;     -- 4 input functions                    ; 116                                                                            ;
;     -- 3 input functions                    ; 36                                                                             ;
;     -- 2 input functions                    ; 105                                                                            ;
;     -- 1 input functions                    ; 26                                                                             ;
;     -- 0 input functions                    ; 57                                                                             ;
;                                             ;                                                                                ;
; Logic elements by mode                      ;                                                                                ;
;     -- normal mode                          ; 276                                                                            ;
;     -- arithmetic mode                      ; 64                                                                             ;
;     -- qfbk mode                            ; 61                                                                             ;
;     -- register cascade mode                ; 0                                                                              ;
;     -- synchronous clear/load mode          ; 110                                                                            ;
;     -- asynchronous clear/load mode         ; 160                                                                            ;
;                                             ;                                                                                ;
; Total LABs                                  ; 44 / 1,206 ( 4 % )                                                             ;
; Logic elements in carry chains              ; 68                                                                             ;
; User inserted logic elements                ; 0                                                                              ;
; Virtual pins                                ; 0                                                                              ;
; I/O pins                                    ; 13 / 173 ( 8 % )                                                               ;
;     -- Clock pins                           ; 1 / 2 ( 50 % )                                                                 ;
; Global signals                              ; 3                                                                              ;
; M4Ks                                        ; 0 / 52 ( 0 % )                                                                 ;
; Total memory bits                           ; 0 / 239,616 ( 0 % )                                                            ;
; Total RAM block bits                        ; 0 / 239,616 ( 0 % )                                                            ;
; PLLs                                        ; 1 / 2 ( 50 % )                                                                 ;
; Global clocks                               ; 3 / 8 ( 38 % )                                                                 ;
; Maximum fan-out node                        ; clockGroups:p_clockGroups_comb|systemPLL:pll_pro|altpll:altpll_component|_clk0 ;
; Maximum fan-out                             ; 197                                                                            ;
; Highest non-global fan-out signal           ; lcd:p_lcd_comb|lcdAddr[1]                                                      ;
; Highest non-global fan-out                  ; 47                                                                             ;
; Total fan-out                               ; 1464                                                                           ;
; Average fan-out                             ; 4.11                                                                           ;
+---------------------------------------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                   ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name   ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+--------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+