📄 pc104_cpld.csf.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "IOW register RegAndIntMode:inst\|IOCtrlReg\[3\] register RegAndIntMode:inst\|IOCtrlReg\[3\] 125.0 MHz 8.0 ns Internal " "Info: Clock IOW has Internal fmax of 125.0 MHz between source register RegAndIntMode:inst\|IOCtrlReg\[3\] and destination register RegAndIntMode:inst\|IOCtrlReg\[3\] (period= 8.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest register register " "Info: + Longest register to register delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns RegAndIntMode:inst\|IOCtrlReg\[3\] 1 REG LC77 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC77; Fanout = 7; REG Node = 'RegAndIntMode:inst\|IOCtrlReg\[3\]'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "" { RegAndIntMode:inst|IOCtrlReg[3] } "NODE_NAME" } } } { "e:/pc104_cpld/RegAndIntMode.vhd" "" "" { Text "e:/pc104_cpld/RegAndIntMode.vhd" 52 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns RegAndIntMode:inst\|IOCtrlReg\[3\] 2 REG LC77 7 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = LC77; Fanout = 7; REG Node = 'RegAndIntMode:inst\|IOCtrlReg\[3\]'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.000 ns" { RegAndIntMode:inst|IOCtrlReg[3] RegAndIntMode:inst|IOCtrlReg[3] } "NODE_NAME" } } } { "e:/pc104_cpld/RegAndIntMode.vhd" "" "" { Text "e:/pc104_cpld/RegAndIntMode.vhd" 52 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 100.00 % " "Info: Total cell delay = 4.000 ns ( 100.00 % )" { } { } 0} } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.000 ns" { RegAndIntMode:inst|IOCtrlReg[3] RegAndIntMode:inst|IOCtrlReg[3] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "IOW destination 4.500 ns + Shortest register " "Info: + Shortest clock path from clock IOW to destination register is 4.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns IOW 1 CLK Pin_40 21 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = Pin_40; Fanout = 21; CLK Node = 'IOW'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "" { IOW } "NODE_NAME" } } } { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 224 -96 72 240 "IOW" "" } { 216 72 106 232 "IOW" "" } { 256 688 776 272 "IOW" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.000 ns) 4.500 ns RegAndIntMode:inst\|IOCtrlReg\[3\] 2 REG LC77 7 " "Info: 2: + IC(1.000 ns) + CELL(3.000 ns) = 4.500 ns; Loc. = LC77; Fanout = 7; REG Node = 'RegAndIntMode:inst\|IOCtrlReg\[3\]'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.000 ns" { IOW RegAndIntMode:inst|IOCtrlReg[3] } "NODE_NAME" } } } { "e:/pc104_cpld/RegAndIntMode.vhd" "" "" { Text "e:/pc104_cpld/RegAndIntMode.vhd" 52 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns 77.78 % " "Info: Total cell delay = 3.500 ns ( 77.78 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 22.22 % " "Info: Total interconnect delay = 1.000 ns ( 22.22 % )" { } { } 0} } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.500 ns" { IOW RegAndIntMode:inst|IOCtrlReg[3] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "IOW source 4.500 ns - Longest register " "Info: - Longest clock path from clock IOW to source register is 4.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns IOW 1 CLK Pin_40 21 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = Pin_40; Fanout = 21; CLK Node = 'IOW'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "" { IOW } "NODE_NAME" } } } { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 224 -96 72 240 "IOW" "" } { 216 72 106 232 "IOW" "" } { 256 688 776 272 "IOW" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.000 ns) 4.500 ns RegAndIntMode:inst\|IOCtrlReg\[3\] 2 REG LC77 7 " "Info: 2: + IC(1.000 ns) + CELL(3.000 ns) = 4.500 ns; Loc. = LC77; Fanout = 7; REG Node = 'RegAndIntMode:inst\|IOCtrlReg\[3\]'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.000 ns" { IOW RegAndIntMode:inst|IOCtrlReg[3] } "NODE_NAME" } } } { "e:/pc104_cpld/RegAndIntMode.vhd" "" "" { Text "e:/pc104_cpld/RegAndIntMode.vhd" 52 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns 77.78 % " "Info: Total cell delay = 3.500 ns ( 77.78 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 22.22 % " "Info: Total interconnect delay = 1.000 ns ( 22.22 % )" { } { } 0} } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.500 ns" { IOW RegAndIntMode:inst|IOCtrlReg[3] } "NODE_NAME" } } } } 0} } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.500 ns" { IOW RegAndIntMode:inst|IOCtrlReg[3] } "NODE_NAME" } } } { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.500 ns" { IOW RegAndIntMode:inst|IOCtrlReg[3] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "e:/pc104_cpld/RegAndIntMode.vhd" "" "" { Text "e:/pc104_cpld/RegAndIntMode.vhd" 52 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "3.000 ns + " "Info: + Micro setup delay of destination is 3.000 ns" { } { { "e:/pc104_cpld/RegAndIntMode.vhd" "" "" { Text "e:/pc104_cpld/RegAndIntMode.vhd" 52 -1 0 } } } 0} } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.000 ns" { RegAndIntMode:inst|IOCtrlReg[3] RegAndIntMode:inst|IOCtrlReg[3] } "NODE_NAME" } } } { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.500 ns" { IOW RegAndIntMode:inst|IOCtrlReg[3] } "NODE_NAME" } } } { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.500 ns" { IOW RegAndIntMode:inst|IOCtrlReg[3] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clk register StartAdMode:inst4\|qn\[0\] register StartAdMode:inst4\|qn\[3\] 76.92 MHz 13.0 ns Internal " "Info: Clock Clk has Internal fmax of 76.92 MHz between source register StartAdMode:inst4\|qn\[0\] and destination register StartAdMode:inst4\|qn\[3\] (period= 13.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.000 ns + Longest register register " "Info: + Longest register to register delay is 9.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns StartAdMode:inst4\|qn\[0\] 1 REG LC39 29 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC39; Fanout = 29; REG Node = 'StartAdMode:inst4\|qn\[0\]'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "" { StartAdMode:inst4|qn[0] } "NODE_NAME" } } } { "E:/Pc104_Cpld/StartAdMode.vhd" "" "" { Text "E:/Pc104_Cpld/StartAdMode.vhd" 38 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(4.000 ns) 5.000 ns StartAdMode:inst4\|lpm_add_sub:i_rtl_1\|addcore:adder\[0\]\|a_csnbuffer:result_node\|sout_node\[3\]~8 2 COMB LC82 3 " "Info: 2: + IC(1.000 ns) + CELL(4.000 ns) = 5.000 ns; Loc. = LC82; Fanout = 3; COMB Node = 'StartAdMode:inst4\|lpm_add_sub:i_rtl_1\|addcore:adder\[0\]\|a_csnbuffer:result_node\|sout_node\[3\]~8'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "5.000 ns" { StartAdMode:inst4|qn[0] StartAdMode:inst4|lpm_add_sub:i_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[3]~8 } "NODE_NAME" } } } { "d:/program files/quartus4.0/libraries/megafunctions/a_csnbuffer.tdf" "" "" { Text "d:/program files/quartus4.0/libraries/megafunctions/a_csnbuffer.tdf" 42 13 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.000 ns) 9.000 ns StartAdMode:inst4\|qn\[3\] 3 REG LC114 29 " "Info: 3: + IC(1.000 ns) + CELL(3.000 ns) = 9.000 ns; Loc. = LC114; Fanout = 29; REG Node = 'StartAdMode:inst4\|qn\[3\]'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.000 ns" { StartAdMode:inst4|lpm_add_sub:i_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[3]~8 StartAdMode:inst4|qn[3] } "NODE_NAME" } } } { "E:/Pc104_Cpld/StartAdMode.vhd" "" "" { Text "E:/Pc104_Cpld/StartAdMode.vhd" 38 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.000 ns 77.78 % " "Info: Total cell delay = 7.000 ns ( 77.78 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 22.22 % " "Info: Total interconnect delay = 2.000 ns ( 22.22 % )" { } { } 0} } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "9.000 ns" { StartAdMode:inst4|qn[0] StartAdMode:inst4|lpm_add_sub:i_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[3]~8 StartAdMode:inst4|qn[3] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 1.500 ns + Shortest register " "Info: + Shortest clock path from clock Clk to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns Clk 1 CLK Pin_87 19 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = Pin_87; Fanout = 19; CLK Node = 'Clk'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "" { Clk } "NODE_NAME" } } } { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 168 1080 1248 184 "Clk" "" } { 232 1280 1320 248 "Clk" "" } { 160 1280 1320 176 "Clk" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns StartAdMode:inst4\|qn\[3\] 2 REG LC114 29 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC114; Fanout = 29; REG Node = 'StartAdMode:inst4\|qn\[3\]'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "0.000 ns" { Clk StartAdMode:inst4|qn[3] } "NODE_NAME" } } } { "E:/Pc104_Cpld/StartAdMode.vhd" "" "" { Text "E:/Pc104_Cpld/StartAdMode.vhd" 38 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" { } { } 0} } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "1.500 ns" { Clk StartAdMode:inst4|qn[3] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 1.500 ns - Longest register " "Info: - Longest clock path from clock Clk to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns Clk 1 CLK Pin_87 19 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = Pin_87; Fanout = 19; CLK Node = 'Clk'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "" { Clk } "NODE_NAME" } } } { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 168 1080 1248 184 "Clk" "" } { 232 1280 1320 248 "Clk" "" } { 160 1280 1320 176 "Clk" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns StartAdMode:inst4\|qn\[0\] 2 REG LC39 29 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC39; Fanout = 29; REG Node = 'StartAdMode:inst4\|qn\[0\]'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "0.000 ns" { Clk StartAdMode:inst4|qn[0] } "NODE_NAME" } } } { "E:/Pc104_Cpld/StartAdMode.vhd" "" "" { Text "E:/Pc104_Cpld/StartAdMode.vhd" 38 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" { } { } 0} } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "1.500 ns" { Clk StartAdMode:inst4|qn[0] } "NODE_NAME" } } } } 0} } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "1.500 ns" { Clk StartAdMode:inst4|qn[3] } "NODE_NAME" } } } { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "1.500 ns" { Clk StartAdMode:inst4|qn[0] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "E:/Pc104_Cpld/StartAdMode.vhd" "" "" { Text "E:/Pc104_Cpld/StartAdMode.vhd" 38 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "3.000 ns + " "Info: + Micro setup delay of destination is 3.000 ns" { } { { "E:/Pc104_Cpld/StartAdMode.vhd" "" "" { Text "E:/Pc104_Cpld/StartAdMode.vhd" 38 -1 0 } } } 0} } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "9.000 ns" { StartAdMode:inst4|qn[0] StartAdMode:inst4|lpm_add_sub:i_rtl_1|addcore:adder[0]|a_csnbuffer:result_node|sout_node[3]~8 StartAdMode:inst4|qn[3] } "NODE_NAME" } } } { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "1.500 ns" { Clk StartAdMode:inst4|qn[3] } "NODE_NAME" } } } { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "1.500 ns" { Clk StartAdMode:inst4|qn[0] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "StartAdMode:inst4\|qn\[3\] IOW Clk 11.800 ns register " "Info: tsu for register StartAdMode:inst4\|qn\[3\] (data pin = IOW, clock pin = Clk) is 11.800 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.300 ns + Longest pin register " "Info: + Longest pin to register delay is 10.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns IOW 1 CLK Pin_40 21 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = Pin_40; Fanout = 21; CLK Node = 'IOW'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "" { IOW } "NODE_NAME" } } } { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 224 -96 72 240 "IOW" "" } { 216 72 106 232 "IOW" "" } { 256 688 776 272 "IOW" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(4.000 ns) 5.500 ns RegAndIntMode:inst\|IOCtrlReg\[0\] 2 REG LC44 41 " "Info: 2: + IC(1.000 ns) + CELL(4.000 ns) = 5.500 ns; Loc. = LC44; Fanout = 41; REG Node = 'RegAndIntMode:inst\|IOCtrlReg\[0\]'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "5.000 ns" { IOW RegAndIntMode:inst|IOCtrlReg[0] } "NODE_NAME" } } } { "e:/pc104_cpld/RegAndIntMode.vhd" "" "" { Text "e:/pc104_cpld/RegAndIntMode.vhd" 52 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.000 ns) 9.500 ns StartAdMode:inst4\|i29~48 3 COMB LC113 1 " "Info: 3: + IC(1.000 ns) + CELL(3.000 ns) = 9.500 ns; Loc. = LC113; Fanout = 1; COMB Node = 'StartAdMode:inst4\|i29~48'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.000 ns" { RegAndIntMode:inst|IOCtrlReg[0] StartAdMode:inst4|i29~48 } "NODE_NAME" } } } { "E:/Pc104_Cpld/StartAdMode.vhd" "" "" { Text "E:/Pc104_Cpld/StartAdMode.vhd" 42 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.800 ns) 10.300 ns StartAdMode:inst4\|qn\[3\] 4 REG LC114 29 " "Info: 4: + IC(0.000 ns) + CELL(0.800 ns) = 10.300 ns; Loc. = LC114; Fanout = 29; REG Node = 'StartAdMode:inst4\|qn\[3\]'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "0.800 ns" { StartAdMode:inst4|i29~48 StartAdMode:inst4|qn[3] } "NODE_NAME" } } } { "E:/Pc104_Cpld/StartAdMode.vhd" "" "" { Text "E:/Pc104_Cpld/StartAdMode.vhd" 38 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.300 ns 80.58 % " "Info: Total cell delay = 8.300 ns ( 80.58 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 19.42 % " "Info: Total interconnect delay = 2.000 ns ( 19.42 % )" { } { } 0} } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "10.300 ns" { IOW RegAndIntMode:inst|IOCtrlReg[0] StartAdMode:inst4|i29~48 StartAdMode:inst4|qn[3] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "3.000 ns + " "Info: + Micro setup delay of destination is 3.000 ns" { } { { "E:/Pc104_Cpld/StartAdMode.vhd" "" "" { Text "E:/Pc104_Cpld/StartAdMode.vhd" 38 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk destination 1.500 ns - Shortest register " "Info: - Shortest clock path from clock Clk to destination register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns Clk 1 CLK Pin_87 19 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = Pin_87; Fanout = 19; CLK Node = 'Clk'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "" { Clk } "NODE_NAME" } } } { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 168 1080 1248 184 "Clk" "" } { 232 1280 1320 248 "Clk" "" } { 160 1280 1320 176 "Clk" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns StartAdMode:inst4\|qn\[3\] 2 REG LC114 29 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC114; Fanout = 29; REG Node = 'StartAdMode:inst4\|qn\[3\]'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "0.000 ns" { Clk StartAdMode:inst4|qn[3] } "NODE_NAME" } } } { "E:/Pc104_Cpld/StartAdMode.vhd" "" "" { Text "E:/Pc104_Cpld/StartAdMode.vhd" 38 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" { } { } 0} } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "1.500 ns" { Clk StartAdMode:inst4|qn[3] } "NODE_NAME" } } } } 0} } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "10.300 ns" { IOW RegAndIntMode:inst|IOCtrlReg[0] StartAdMode:inst4|i29~48 StartAdMode:inst4|qn[3] } "NODE_NAME" } } } { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "1.500 ns" { Clk StartAdMode:inst4|qn[3] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Clk ReadAd\[0\] AdToFifo:inst6\|lpm_counter:qn_rtl_0\|dffs\[1\] 15.800 ns register " "Info: tco from clock Clk to destination pin ReadAd\[0\] through register AdToFifo:inst6\|lpm_counter:qn_rtl_0\|dffs\[1\] is 15.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 1.500 ns + Longest register " "Info: + Longest clock path from clock Clk to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns Clk 1 CLK Pin_87 19 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = Pin_87; Fanout = 19; CLK Node = 'Clk'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "" { Clk } "NODE_NAME" } } } { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 168 1080 1248 184 "Clk" "" } { 232 1280 1320 248 "Clk" "" } { 160 1280 1320 176 "Clk" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns AdToFifo:inst6\|lpm_counter:qn_rtl_0\|dffs\[1\] 2 REG LC31 12 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC31; Fanout = 12; REG Node = 'AdToFifo:inst6\|lpm_counter:qn_rtl_0\|dffs\[1\]'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "0.000 ns" { Clk AdToFifo:inst6|lpm_counter:qn_rtl_0|dffs[1] } "NODE_NAME" } } } { "d:/program files/quartus4.0/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "d:/program files/quartus4.0/libraries/megafunctions/lpm_counter.tdf" 256 9 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" { } { } 0} } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "1.500 ns" { Clk AdToFifo:inst6|lpm_counter:qn_rtl_0|dffs[1] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "d:/program files/quartus4.0/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "d:/program files/quartus4.0/libraries/megafunctions/lpm_counter.tdf" 256 9 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.300 ns + Longest register pin " "Info: + Longest register to pin delay is 13.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns AdToFifo:inst6\|lpm_counter:qn_rtl_0\|dffs\[1\] 1 REG LC31 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC31; Fanout = 12; REG Node = 'AdToFifo:inst6\|lpm_counter:qn_rtl_0\|dffs\[1\]'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "" { AdToFifo:inst6|lpm_counter:qn_rtl_0|dffs[1] } "NODE_NAME" } } } { "d:/program files/quartus4.0/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "d:/program files/quartus4.0/libraries/megafunctions/lpm_counter.tdf" 256 9 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.000 ns) 4.000 ns AdToFifo:inst6\|i72~125 2 COMB LC18 1 " "Info: 2: + IC(1.000 ns) + CELL(3.000 ns) = 4.000 ns; Loc. = LC18; Fanout = 1; COMB Node = 'AdToFifo:inst6\|i72~125'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.000 ns" { AdToFifo:inst6|lpm_counter:qn_rtl_0|dffs[1] AdToFifo:inst6|i72~125 } "NODE_NAME" } } } { "E:/Pc104_Cpld/AdToFifo.vhd" "" "" { Text "E:/Pc104_Cpld/AdToFifo.vhd" 50 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 5.800 ns AdToFifo:inst6\|i72~123 3 COMB LC19 8 " "Info: 3: + IC(0.000 ns) + CELL(1.800 ns) = 5.800 ns; Loc. = LC19; Fanout = 8; COMB Node = 'AdToFifo:inst6\|i72~123'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "1.800 ns" { AdToFifo:inst6|i72~125 AdToFifo:inst6|i72~123 } "NODE_NAME" } } } { "E:/Pc104_Cpld/AdToFifo.vhd" "" "" { Text "E:/Pc104_Cpld/AdToFifo.vhd" 50 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(4.000 ns) 10.800 ns AdToFifo:inst6\|i88~8 4 COMB LC16 1 " "Info: 4: + IC(1.000 ns) + CELL(4.000 ns) = 10.800 ns; Loc. = LC16; Fanout = 1; COMB Node = 'AdToFifo:inst6\|i88~8'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "5.000 ns" { AdToFifo:inst6|i72~123 AdToFifo:inst6|i88~8 } "NODE_NAME" } } } { "E:/Pc104_Cpld/AdToFifo.vhd" "" "" { Text "E:/Pc104_Cpld/AdToFifo.vhd" 72 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 13.300 ns ReadAd\[0\] 5 PIN Pin_92 0 " "Info: 5: + IC(0.000 ns) + CELL(2.500 ns) = 13.300 ns; Loc. = Pin_92; Fanout = 0; PIN Node = 'ReadAd\[0\]'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "2.500 ns" { AdToFifo:inst6|i88~8 ReadAd[0] } "NODE_NAME" } } } { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 232 1584 1760 248 "ReadAd\[3..0\]" "" } { 224 1520 1594 240 "ReadAd\[3..0\]" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.300 ns 84.96 % " "Info: Total cell delay = 11.300 ns ( 84.96 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 15.04 % " "Info: Total interconnect delay = 2.000 ns ( 15.04 % )" { } { } 0} } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "13.300 ns" { AdToFifo:inst6|lpm_counter:qn_rtl_0|dffs[1] AdToFifo:inst6|i72~125 AdToFifo:inst6|i72~123 AdToFifo:inst6|i88~8 ReadAd[0] } "NODE_NAME" } } } } 0} } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "1.500 ns" { Clk AdToFifo:inst6|lpm_counter:qn_rtl_0|dffs[1] } "NODE_NAME" } } } { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "13.300 ns" { AdToFifo:inst6|lpm_counter:qn_rtl_0|dffs[1] AdToFifo:inst6|i72~125 AdToFifo:inst6|i72~123 AdToFifo:inst6|i88~8 ReadAd[0] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "AEN ReadAd\[0\] 13.800 ns Longest " "Info: Longest tpd from source pin AEN to destination pin ReadAd\[0\] is 13.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns AEN 1 PIN Pin_37 57 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = Pin_37; Fanout = 57; PIN Node = 'AEN'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "" { AEN } "NODE_NAME" } } } { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 72 -96 72 88 "AEN" "" } { 64 72 136 80 "AEN" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.000 ns) 4.500 ns AdToFifo:inst6\|i72~125 2 COMB LC18 1 " "Info: 2: + IC(1.000 ns) + CELL(3.000 ns) = 4.500 ns; Loc. = LC18; Fanout = 1; COMB Node = 'AdToFifo:inst6\|i72~125'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.000 ns" { AEN AdToFifo:inst6|i72~125 } "NODE_NAME" } } } { "E:/Pc104_Cpld/AdToFifo.vhd" "" "" { Text "E:/Pc104_Cpld/AdToFifo.vhd" 50 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 6.300 ns AdToFifo:inst6\|i72~123 3 COMB LC19 8 " "Info: 3: + IC(0.000 ns) + CELL(1.800 ns) = 6.300 ns; Loc. = LC19; Fanout = 8; COMB Node = 'AdToFifo:inst6\|i72~123'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "1.800 ns" { AdToFifo:inst6|i72~125 AdToFifo:inst6|i72~123 } "NODE_NAME" } } } { "E:/Pc104_Cpld/AdToFifo.vhd" "" "" { Text "E:/Pc104_Cpld/AdToFifo.vhd" 50 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(4.000 ns) 11.300 ns AdToFifo:inst6\|i88~8 4 COMB LC16 1 " "Info: 4: + IC(1.000 ns) + CELL(4.000 ns) = 11.300 ns; Loc. = LC16; Fanout = 1; COMB Node = 'AdToFifo:inst6\|i88~8'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "5.000 ns" { AdToFifo:inst6|i72~123 AdToFifo:inst6|i88~8 } "NODE_NAME" } } } { "E:/Pc104_Cpld/AdToFifo.vhd" "" "" { Text "E:/Pc104_Cpld/AdToFifo.vhd" 72 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 13.800 ns ReadAd\[0\] 5 PIN Pin_92 0 " "Info: 5: + IC(0.000 ns) + CELL(2.500 ns) = 13.800 ns; Loc. = Pin_92; Fanout = 0; PIN Node = 'ReadAd\[0\]'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "2.500 ns" { AdToFifo:inst6|i88~8 ReadAd[0] } "NODE_NAME" } } } { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 232 1584 1760 248 "ReadAd\[3..0\]" "" } { 224 1520 1594 240 "ReadAd\[3..0\]" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.800 ns 85.51 % " "Info: Total cell delay = 11.800 ns ( 85.51 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 14.49 % " "Info: Total interconnect delay = 2.000 ns ( 14.49 % )" { } { } 0} } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "13.800 ns" { AEN AdToFifo:inst6|i72~125 AdToFifo:inst6|i72~123 AdToFifo:inst6|i88~8 ReadAd[0] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_TH_RESULT" "RegAndIntMode:inst\|IntEnReg\[3\] DataBus\[3\] IOW 2.000 ns register " "Info: th for register RegAndIntMode:inst\|IntEnReg\[3\] (data pin = DataBus\[3\], clock pin = IOW) is 2.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "IOW destination 4.500 ns + Longest register " "Info: + Longest clock path from clock IOW to destination register is 4.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns IOW 1 CLK Pin_40 21 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = Pin_40; Fanout = 21; CLK Node = 'IOW'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "" { IOW } "NODE_NAME" } } } { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 224 -96 72 240 "IOW" "" } { 216 72 106 232 "IOW" "" } { 256 688 776 272 "IOW" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.000 ns) 4.500 ns RegAndIntMode:inst\|IntEnReg\[3\] 2 REG LC69 5 " "Info: 2: + IC(1.000 ns) + CELL(3.000 ns) = 4.500 ns; Loc. = LC69; Fanout = 5; REG Node = 'RegAndIntMode:inst\|IntEnReg\[3\]'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.000 ns" { IOW RegAndIntMode:inst|IntEnReg[3] } "NODE_NAME" } } } { "e:/pc104_cpld/RegAndIntMode.vhd" "" "" { Text "e:/pc104_cpld/RegAndIntMode.vhd" 52 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns 77.78 % " "Info: Total cell delay = 3.500 ns ( 77.78 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 22.22 % " "Info: Total interconnect delay = 1.000 ns ( 22.22 % )" { } { } 0} } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.500 ns" { IOW RegAndIntMode:inst|IntEnReg[3] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "2.000 ns + " "Info: + Micro hold delay of destination is 2.000 ns" { } { { "e:/pc104_cpld/RegAndIntMode.vhd" "" "" { Text "e:/pc104_cpld/RegAndIntMode.vhd" 52 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.500 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DataBus\[3\] 1 PIN Pin_31 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = Pin_31; Fanout = 1; PIN Node = 'DataBus\[3\]'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "" { DataBus[3] } "NODE_NAME" } } } { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 208 560 736 224 "DataBus\[7..0\]" "" } { 200 736 804 216 "DataBus\[7..0\]" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns DataBus~4 2 COMB IO57 4 " "Info: 2: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = IO57; Fanout = 4; COMB Node = 'DataBus~4'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "0.500 ns" { DataBus[3] DataBus~4 } "NODE_NAME" } } } { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 208 560 736 224 "DataBus\[7..0\]" "" } { 200 736 804 216 "DataBus\[7..0\]" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(3.000 ns) 4.500 ns RegAndIntMode:inst\|IntEnReg\[3\] 3 REG LC69 5 " "Info: 3: + IC(1.000 ns) + CELL(3.000 ns) = 4.500 ns; Loc. = LC69; Fanout = 5; REG Node = 'RegAndIntMode:inst\|IntEnReg\[3\]'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.000 ns" { DataBus~4 RegAndIntMode:inst|IntEnReg[3] } "NODE_NAME" } } } { "e:/pc104_cpld/RegAndIntMode.vhd" "" "" { Text "e:/pc104_cpld/RegAndIntMode.vhd" 52 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.500 ns 77.78 % " "Info: Total cell delay = 3.500 ns ( 77.78 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 22.22 % " "Info: Total interconnect delay = 1.000 ns ( 22.22 % )" { } { } 0} } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.500 ns" { DataBus[3] DataBus~4 RegAndIntMode:inst|IntEnReg[3] } "NODE_NAME" } } } } 0} } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.500 ns" { IOW RegAndIntMode:inst|IntEnReg[3] } "NODE_NAME" } } } { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "4.500 ns" { DataBus[3] DataBus~4 RegAndIntMode:inst|IntEnReg[3] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "Clk ChannelVector\[0\] AdToFifo:inst6\|lpm_counter:qn_rtl_0\|dffs\[4\] 5.000 ns register " "Info: Minimum tco from clock Clk to destination pin ChannelVector\[0\] through register AdToFifo:inst6\|lpm_counter:qn_rtl_0\|dffs\[4\] is 5.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk source 1.500 ns + Shortest register " "Info: + Shortest clock path from clock Clk to source register is 1.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns Clk 1 CLK Pin_87 19 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = Pin_87; Fanout = 19; CLK Node = 'Clk'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "" { Clk } "NODE_NAME" } } } { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 168 1080 1248 184 "Clk" "" } { 232 1280 1320 248 "Clk" "" } { 160 1280 1320 176 "Clk" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 1.500 ns AdToFifo:inst6\|lpm_counter:qn_rtl_0\|dffs\[4\] 2 REG LC29 6 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 1.500 ns; Loc. = LC29; Fanout = 6; REG Node = 'AdToFifo:inst6\|lpm_counter:qn_rtl_0\|dffs\[4\]'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "0.000 ns" { Clk AdToFifo:inst6|lpm_counter:qn_rtl_0|dffs[4] } "NODE_NAME" } } } { "d:/program files/quartus4.0/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "d:/program files/quartus4.0/libraries/megafunctions/lpm_counter.tdf" 256 9 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns 100.00 % " "Info: Total cell delay = 1.500 ns ( 100.00 % )" { } { } 0} } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "1.500 ns" { Clk AdToFifo:inst6|lpm_counter:qn_rtl_0|dffs[4] } "NODE_NAME" } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" { } { { "d:/program files/quartus4.0/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "d:/program files/quartus4.0/libraries/megafunctions/lpm_counter.tdf" 256 9 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.500 ns + Shortest register pin " "Info: + Shortest register to pin delay is 2.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns AdToFifo:inst6\|lpm_counter:qn_rtl_0\|dffs\[4\] 1 REG LC29 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC29; Fanout = 6; REG Node = 'AdToFifo:inst6\|lpm_counter:qn_rtl_0\|dffs\[4\]'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "" { AdToFifo:inst6|lpm_counter:qn_rtl_0|dffs[4] } "NODE_NAME" } } } { "d:/program files/quartus4.0/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "d:/program files/quartus4.0/libraries/megafunctions/lpm_counter.tdf" 256 9 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 2.500 ns ChannelVector\[0\] 2 PIN Pin_6 0 " "Info: 2: + IC(0.000 ns) + CELL(2.500 ns) = 2.500 ns; Loc. = Pin_6; Fanout = 0; PIN Node = 'ChannelVector\[0\]'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "2.500 ns" { AdToFifo:inst6|lpm_counter:qn_rtl_0|dffs[4] ChannelVector[0] } "NODE_NAME" } } } { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 272 1584 1776 288 "ChannelVector\[3..0\]" "" } { 264 1520 1617 280 "ChannelVector\[3..0\]" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns 100.00 % " "Info: Total cell delay = 2.500 ns ( 100.00 % )" { } { } 0} } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "2.500 ns" { AdToFifo:inst6|lpm_counter:qn_rtl_0|dffs[4] ChannelVector[0] } "NODE_NAME" } } } } 0} } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "1.500 ns" { Clk AdToFifo:inst6|lpm_counter:qn_rtl_0|dffs[4] } "NODE_NAME" } } } { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "2.500 ns" { AdToFifo:inst6|lpm_counter:qn_rtl_0|dffs[4] ChannelVector[0] } "NODE_NAME" } } } } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "SA\[8\] CS_D 8.000 ns Shortest " "Info: Shortest tpd from source pin SA\[8\] to destination pin CS_D is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns SA\[8\] 1 PIN Pin_44 74 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = Pin_44; Fanout = 74; PIN Node = 'SA\[8\]'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "" { SA[8] } "NODE_NAME" } } } { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 24 -96 72 40 "SA\[9..0\]" "" } { 16 72 136 32 "SA\[9..0\]" "" } } } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(4.000 ns) 5.500 ns AddressDecoder:inst3\|i15~13 2 COMB LC33 1 " "Info: 2: + IC(1.000 ns) + CELL(4.000 ns) = 5.500 ns; Loc. = LC33; Fanout = 1; COMB Node = 'AddressDecoder:inst3\|i15~13'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "5.000 ns" { SA[8] AddressDecoder:inst3|i15~13 } "NODE_NAME" } } } { "e:/pc104_cpld/AddressDecoder.vhd" "" "" { Text "e:/pc104_cpld/AddressDecoder.vhd" 40 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.500 ns) 8.000 ns CS_D 3 PIN Pin_25 0 " "Info: 3: + IC(0.000 ns) + CELL(2.500 ns) = 8.000 ns; Loc. = Pin_25; Fanout = 0; PIN Node = 'CS_D'" { } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "2.500 ns" { AddressDecoder:inst3|i15~13 CS_D } "NODE_NAME" } } } { "E:/Pc104_Cpld/Pc104_Cpld.bdf" "" "" { Schematic "E:/Pc104_Cpld/Pc104_Cpld.bdf" { { 184 376 552 200 "CS_D" "" } { 176 312 376 192 "CS_D" "" } } } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.000 ns 87.50 % " "Info: Total cell delay = 7.000 ns ( 87.50 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.000 ns 12.50 % " "Info: Total interconnect delay = 1.000 ns ( 12.50 % )" { } { } 0} } { { "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" "" "" { Report "E:/Pc104_Cpld/db/Pc104_Cpld_cmp.qrpt" Compiler "Pc104_Cpld" "UNKNOWN" "V1" "E:/Pc104_Cpld/db/Pc104_Cpld.quartus_db" { Floorplan "" "" "8.000 ns" { SA[8] AddressDecoder:inst3|i15~13 CS_D } "NODE_NAME" } } } } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1 " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 11 14:08:26 2006 " "Info: Processing ended: Thu May 11 14:08:26 2006" { } { } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0} } { } 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 5 s " "Info: Quartus II Full Compilation was successful. 0 errors, 5 warnings" { } { } 0}
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