pc104_cpld.map.rpt

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Analysis & Synthesis report for Pc104_Cpld
Thu May 11 14:08:18 2006
Version 4.0 Build 190 1/28/2004 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Default Parameter Settings
  5. Hierarchy
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis Equations
  8. Analysis & Synthesis Files Read
  9. Analysis & Synthesis Resource Usage Summary
 10. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



+---------------------------------------------------------------------+
; Analysis & Synthesis Summary                                        ;
+-----------------------------+---------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu May 11 14:08:18 2006 ;
; Revision Name               ; Pc104_Cpld                            ;
; Top-level Entity Name       ; Pc104_Cpld                            ;
; Family                      ; MAX7000S                              ;
; Total macrocells            ; 69                                    ;
; Total pins                  ; 51                                    ;
+-----------------------------+---------------------------------------+


+-----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                       ;
+------------------------------------------------------------------------------------------------------
; Option                                                               ; Setting      ; Default Value ;
+----------------------------------------------------------------------+--------------+---------------+
; Top-level entity name                                                ; Pc104_Cpld   ;               ;
; Family name                                                          ; MAX7000S     ; Stratix       ;
; Auto Resource Sharing                                                ; Off          ; Off           ;
; Remove Duplicate Logic                                               ; On           ; On            ;
; Auto Open-Drain Pins                                                 ; On           ; On            ;
; Auto Parallel Expanders                                              ; On           ; On            ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4            ; 4             ;
; Auto Logic Cell Insertion                                            ; On           ; On            ;
; Allow XOR Gate Usage                                                 ; On           ; On            ;
; Optimization Technique -- MAX 7000B/7000AE/3000A                     ; Speed        ; Speed         ;
; Limit AHDL Integers to 32 Bits                                       ; Off          ; Off           ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A            ; Off          ; Off           ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A           ; Auto         ; Auto          ;
; Ignore ROW GLOBAL Buffers                                            ; Off          ; Off           ;
; Ignore GLOBAL Buffers                                                ; Off          ; Off           ;
; Ignore CASCADE Buffers                                               ; Off          ; Off           ;
; Ignore CARRY Buffers                                                 ; Off          ; Off           ;
; Remove Duplicate Registers                                           ; On           ; On            ;
; Remove Redundant Logic Cells                                         ; Off          ; Off           ;
; Power-Up Don't Care                                                  ; On           ; On            ;
; NOT Gate Push-Back                                                   ; On           ; On            ;
; State Machine Processing                                             ; Auto         ; Auto          ;
; VHDL Version                                                         ; VHDL93       ; VHDL93        ;
; Verilog Version                                                      ; Verilog_2001 ; Verilog_2001  ;
; Preserve fewer node names                                            ; On           ; On            ;
; Disk space/compilation speed tradeoff                                ; Normal       ; Normal        ;
; Create Debugging Nodes for IP Cores                                  ; off          ; off           ;
+----------------------------------------------------------------------+--------------+---------------+


+-------------------------------------------------+
; Analysis & Synthesis Default Parameter Settings ;
+--------------------------------------------------
; Name               ; Setting                    ;
+--------------------+----------------------------+
; CARRY_CHAIN        ; MANUAL                     ;
; CASCADE_CHAIN      ; MANUAL                     ;
; OPTIMIZE_FOR_SPEED ; 9                          ;
; STYLE              ; FAST                       ;
+--------------------+----------------------------+


+------------+
; Hierarchy  ;
+------------+
Pc104_Cpld
 |-- RegAndIntMode:inst
 |-- AddressDecoder:inst3
 |-- StartAdMode:inst4
      |-- lpm_add_sub:i_rtl_1
           |-- addcore:adder
           |-- addcore:adder[0]
                |-- a_csnbuffer:cout_node
                |-- a_csnbuffer:oflow_node
                |-- a_csnbuffer:result_node
           |-- addcore:adder[1]
                |-- a_csnbuffer:cout_node
                |-- a_csnbuffer:oflow_node
                |-- a_csnbuffer:result_node
           |-- altshift:carry_ext_latency_ffs
           |-- look_add:look_ahead_unit